DATA SHEET - IEETA

Philips Semiconductors Product specification
8-bit microcontroller with on-chip CAN P8xC592
BIT SYMBOL FUNCTION
5 RA Reference Active (notes 2). If the value of RA is:
Notes to the description of the CR bits
1. The test mode is intended for factory testing and not for customer use.
2. A modification of the bits Reference Active and Sync is only possible with Reset Request = HIGH (present). It is
allowed to set these bits while Reset Request is changed from a HIGH level to a LOW level. After an external reset
(pin RST = HIGH) the Reference Active bit is set HIGH (output), the Sync bit is undefined.
3. During an external reset (RST = HIGH) or when the Bus Status bit is set HIGH (Bus-OFF), the IML forces the
Reset Request HIGH (present). After the Reset Request bit is set LOW (absent) the CAN-controller will wait for:
a) One occurrence of the Bus-Free signal (11 recessive bits, see Section 13.6.9.6), if the preceding reset (Reset
Request = HIGH) has been caused by an external reset or a CPU initiated reset.
b) 128 occurrences of Bus-Free, if the preceding reset (Reset Request = HIGH) has been caused by a
CAN-controller initiated Bus-OFF, before re-entering the Bus-On mode, see Section 13.6.9.
c) When Reset Request is set HIGH (present), for whatever reason, the Control, Command, Status and Interrupt
bits are affected, see Table 40. The registers at addresses 4 to 8 are only accessible when the Reset Request is
set HIGH (present).
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HIGH (output), then the pin REF is an 1 ⁄2AVDD reference output.
4 OIE
LOW (input), then a reference voltage may be input.
Overrun Interrupt Enable. If the value of OIE is:
HIGH (enabled) and the Data Overrun bit is set (see Section 13.5.5) then the CPU
receives an Overrun Interrupt signal.
LOW (disabled), then the CPU receives no Overrun Interrupt signal from the
CAN-controller.
3 EIE Error Interrupt Enable. If the value of EIE is:
HIGH (enabled) and the Error or Bus Status change (see Section 13.5.5) then the CPU
receives an Error Interrupt signal.
LOW (disabled), then the CPU receives no Error Interrupt signal.
2 TIE Transmit Interrupt Enable. If the value of TIE is:
HIGH (enabled) and when a message has been successfully transmitted or the
Transmit Buffer is accessible again, (e.g. after an Abort Transmission command), then
the CAN-controller transmits a Transmit Interrupt signal to the CPU.
LOW (disabled), then there is no transmission of the Transmit Interrupt signal by the
CAN-controller to the CPU.
1 RIE Receive Interrupt Enable. If the value of RIE is:
HIGH (enabled) and when a message has been received without errors, then the
CAN-controller transmits a Receive Interrupt signal to the CPU.
LOW (disabled), then there is no transmission of the Receive Interrupt signal by the
CAN-controller to the CPU.
0 RR Reset Request (note 3). If the value of RR is:
HIGH (present), then detection of a Reset Request results in the CAN-controller
aborting the current transmission/reception of a message entering the reset state
synchronously to the system clock (tSCL, see Section 13.5.9).
LOW (absent), on the HIGH-to-LOW transition of the Reset Request bit, the
CAN-controller returns to its normal operating state.