DATA SHEET - IEETA

More documents

Recommendations

Info

Philips Semiconductors Product specification 8-bit microcontroller with on-chip CAN P8xC592 handbook, full pagewidth code out 1023 1022 1021 1020 1019 1018 (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential non-linearity (DLe). (4) Integral non-linearity (ILe). (5) Centre of a step of the actual transfer curve. 7 6 5 4 3 2 1 0 offset error OS e 1 LSB (ideal) 1 2 3 4 5 6 7 1018 1019 1020 1021 1022 1023 1024 Fig.28 ADC conversion characteristic. 1996 Jun 27 84 (4) (2) (5) (3) offset error OS e (1) 1 LSB ideal = AVIN (LSBideal ) AVREF+ −AVREF− 1024 gain error Ge MGA173
Philips Semiconductors Product specification 8-bit microcontroller with on-chip CAN P8xC592 21 AC CHARACTERISTICS See notes 1 and 2; CL = 100 pF for Port 0, ALE and PSEN; CL = 80 pF for all other outputs unless otherwise specified. SYMBOL PARAMETER External Program Memory Notes 1. For the AC Characteristics the following conditions are valid: P8xC592 FFA (FHA): VDD =5V±10%; Tamb = −40 to +85 °C (125 °C); fCLK = 1.2 to 16 MHz. 2. = 1 ---------- = one oscillator clock period ; tCLK = 62.5 ns at fCLK = 16 MHz. 1996 Jun 27 85 fCLK = 16 MHz fCLK = 12 MHz VARIABLE CLOCK 1.2 to 16 MHz UNIT MIN. MAX. MIN. MAX. MIN. MAX. tLHLL ALE pulse width 85 − 127 − 2tCLK − 40 − ns tAVLL address valid to ALE LOW 23 − 43 − tCLK − 40 − ns tLLAX address hold after ALE LOW 33 − 53 − tCLK − 30 − ns tLLIV ALE LOW to valid instruction in − 150 − 233 − 4tCLK − 100 ns tLLPL ALE LOW to PSEN LOW 33 − 53 − tCLK − 30 − ns tPLPH PSEN pulse width 143 − 205 − 3tCLK − 45 − ns tPLIV PSEN LOW to valid instruction in − 83 − 145 − 3tCLK − 105 ns tPXIX input instruction hold after PSEN 0 − 0 − 0 − ns tPXIZ input instruction float after PSEN − 38 − 59 − tCLK − 25 ns tAVIV address to valid instruction in − 208 − 312 − 5tCLK − 105 ns tPLAZ PSEN LOW to address float − 10 − 10 − 10 ns External data memory tRLRH RD pulse width 275 − 400 − 6tCLK − 100 − ns tWLWH WR pulse width 275 − 400 − 6tCLK − 100 − ns tAVLL address valid to ALE LOW 8 − 28 − tCLK − 55 − ns tLLAX address hold after ALE LOW 33 − 53 − tCLK − 30 − ns tRLDV RD LOW to valid data in − 148 − 252 − 5tCLK −165 ns tRHDX data hold after RD 0 − 0 − 0 − ns tRHDZ data float after RD − 55 − 97 − 2tCLK − 70 ns tLLDV ALE LOW to valid data in − 350 − 517 − 8tCLK − 150 ns tAVDV address to valid data in − 398 − 585 − 9tCLK − 165 ns tLLWL ALE LOW to RD or WR LOW 138 238 200 300 3tCLK − 50 3tCLK +50 ns tAVWL address valid to RD or WR LOW 120 − 203 − 4tCLK − 130 − ns tWHLH RD or WR HIGH to ALE HIGH 23 103 43 123 tCLK − 40 tCLK +40 ns tQVWX data valid to WR transition 13 − 33 − tCLK − 50 − ns tQVWH data valid time WR HIGH 288 − 433 − 7tCLK − 150 − ns tWHQX data hold after WR 13 − 33 − tCLK − 50 − ns tRLAZ RD LOW to address float − 0 − 0 − 0 ns t CLK f CLK
Page 1 and 2:
DATA SHEET Product specification Su
Page 3 and 4:
Philips Semiconductors Product spec
Page 5 and 6:
Page 7 and 8:
Page 9 and 10:
Page 11 and 12:
Page 13 and 14:
Page 15 and 16:
Page 17 and 18:
Page 19 and 20:
Page 21 and 22:
Page 23 and 24:
Page 25 and 26:
Page 27 and 28:
Page 29 and 30:
Page 31 and 32:
Page 33 and 34: Philips Semiconductors Product spec
Page 83: Philips Semiconductors Product spec
show all

DATA SHEET - IEETA

You also want an ePaper? Increase the reach of your titles

Delete template?

Save as template?