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Philips Semiconductors Product specification 8-bit microcontroller with on-chip CAN P8xC592 handbook, full pagewidth interrupt interrupt enable registers sources source enable global enable INT0 CT0I INT1 CT1I CT2I CT3I EXTERNAL INTERRUPT REQUEST 0 CAN SERIAL PORT 1 ADC TIMER 0 OVERFLOW TIMER 2 CAPTURE 0 TIMER 2 COMPARE 0 EXTERNAL INTERRUPT REQUEST 1 TIMER 2 CAPTURE 1 TIMER 2 COMPARE 1 TIMER 1 OVERFLOW TIMER 2 CAPTURE 2 TIMER 2 COMPARE 2 UART SERIAL PORT 0 T R TIMER 2 CAPTURE 3 TIMER T2 OVERFLOW Fig.21 Interrupt system. 1996 Jun 27 64 interrupt priority registers a1 a2 b1 b2 c1 c2 d1 d2 e1 e2 f1 f2 g1 g2 h1 h2 i1 i2 j1 j2 k1 k2 l1 l2 m1 m2 n1 n2 o1 o2 a1 b1 c1 d1 e1 f1 g1 h1 i1 j1 k1 l1 m1 n1 o1 a2 b2 c2 d2 e2 f2 g2 h2 i2 j2 k2 l2 m2 n2 o2 polling hardware SOURCE IDENTIFICATION SOURCE IDENTIFICATION MGA166 high priority interrupt request vector low priority interrupt request vector
Philips Semiconductors Product specification 8-bit microcontroller with on-chip CAN P8xC592 14.1 Interrupt Enable and Priority Registers 14.1.1 INTERRUPT ENABLE REGISTER 0 (IEN0) Table 71 Interrupt Enable register 0 (address A8H) 7 6 5 4 3 2 1 0 EA EAD ES1 ES0 ET1 EX1 ET0 EX0 Table 72 Description of the IEN0 bits BIT SYMBOL FUNCTION 7 EA General enable/disable control. If bit EA is: LOW, then no interrupt is enabled. HIGH, then any individually enabled interrupt will be accepted. 6 EAD Enable ADC interrupt. 5 ES1 Enable SIO1 (CAN) interrupt. 4 ES0 Enable SIO0 (UART) interrupt. 3 ET1 Enable Timer 1 interrupt. 2 EX1 Enable External 1 interrupt. 1 ET0 Enable Timer 0 interrupt. 0 EX0 Enable External 0 interrupt. 14.1.2 INTERRUPT ENABLE REGISTER 1 (IEN1) Table 73 Interrupt Enable register 0 (address E8H) 7 6 5 4 3 2 1 0 ET2 ECM2 ECM1 ECM0 ECT3 ECT2 ECT1 ECT0 Table 74 Description of the IEN1 bits Logic 0 = interrupt disabled; Logic 1 = interrupt enabled. BIT SYMBOL FUNCTION 7 ET2 Enable T2 overflow interrupt(s). 6 ECM2 Enable T2 comparator 2 interrupt. 5 ECM1 Enable T2 comparator 1 interrupt. 4 ECM0 Enable T2 comparator 0 interrupt. 3 ECT3 Enable T2 capture register 3 interrupt. 2 ECT1 Enable T2 capture register 2 interrupt. 1 ECT1 Enable T2 capture register 1 interrupt. 0 ECT0 Enable T2 capture register 0 interrupt. 1996 Jun 27 65
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