PhD Thesis - Cranfield University

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Chapter 7 Power Losses in the PE switch and diode Table 7.5 Converter power electronic device parameters The MOSFET conduction loss during forward conduction (ON-State) is a function of the duty cycle D, and can be calculated as, P con where ⎛ ⎜ 1 = i ⎜ ⎝ t ∫ on ton = I 2 out sw ⋅ Rds ⎞ ( t) dt ⎟ ⎟ ⎠ ( on) 2 ⋅ D Rds ( on) ⋅ D Rds (on) is the MOSFET ON- resistance 205 (7-81) The switching losses are influenced by the intrinsic MOSFET turn-on time delay t sw(on) and turn-off time delay t sw(off) according to, 1 P sw = I ds ⋅VDC ( peak ) ⋅ f sw ⋅ ( t sw( on) + tsw( off ) ) (7-82) 2 where Device Voltage rating Current rating Physical Device Configuration Switches T1, T2, T3, T4 Diodes D1, D2, D3, D4 Vpeak = 70V Vpeak = 70V Ipeak = 250A Ipeak = 250A I ds is the MOSFET drain to source current MOSFET IRFB 4710 100V, 75A , Rds =0.014ohm Ultra Fast Diode IR- 70EPF02 200V, 600A, Vfd=1.4V 4 units in parallel for each switch set (16 units in total) 1 unit per switch set.
Chapter 7 During the MOSFET diode conduction state, current flowing through the diode develops a forward voltage drop, which dissipates power according to P diode ⎛ 1 = ∆V ⎜ diode i ⎜ t ∫ off ⎝ toff = ∆V diode ⋅ I out out ⋅ ( 1− D) ⎞ ( t) dt ⎟ ⋅ ( 1− D) ⎟ ⎠ 206 (7-83) where t off corresponds to the OFF time of the complementary MOSFET connected in series with the diode. For example, the power loss due to current flowing through diode D1 is calculated based on the OFF time of switch T2. Therefore the average power loss for a MOSFET-Diode pair during a switching interval is, P sw = P + P + P (7-84) Loss con sw diode Power loss as a function of system SoC and power output The effect of the converter power loss just described can be demonstrated in the context of a power and energy management system as follows. Figure 7.12 shows the converter power loss as a function of the battery and ultracapacitor power flow and corresponding battery and ultracapacitor state of charge. As shown, the power loss when ultracapacitor power is transferred increases as the ultracapacitor SoC decreases. This is due to the voltage decay of the ultracapacitors as the SoC reduces. Comparatively, the battery power loss is less influenced by the decrease in its SoC. As such, discharging the ultracapacitors at high current during a low state of charge results in a high power loss. So, although ultracapacitors are excellent as a peak power buffer, this cost in terms of power transfer efficiency via the converter needs to be considered.
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Power and Energy Management of Mult
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Acknowledgements This journey would
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Nomenclature Notation Description U
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Abbreviations Batt (batt) Battery D
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Contents 3.19 Ultracapacitor Power
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List of Figures List of Figures Fig
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List of Figures Figure 6.3 Power de
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Chapter 1 CHAPTER 1 INTRODUCTION
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Chapter 1 more than a century since
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Chapter 1 EV Charge Depleting Energ
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Chapter 1 1745 Invention of the cap
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Chapter 1 generated, and split betw
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Chapter 1 In the past, many researc
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Chapter 1 1.7 Contributions This th
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Chapter 1 7. As the hybridisation o
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Chapter 1 1.9 Publications The foll
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Chapter 2 CHAPTER 2 LITERATURE REVI
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Chapter 2 in the area or power and
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Chapter 2 Power Load Demand Time Po
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Chapter 2 previewed information abo
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Chapter 2 generally used. They are,
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Chapter 2 the large capacitive phen
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Chapter 2 manufacturer. Throughout
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Chapter 2 energy density attributes
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Chapter 2 experimentally verified a
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Chapter 2 Propulsion Load Batteries
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Chapter 2 system. They compared the
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Chapter 2 2.6 Ultracapacitor augmen
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Chapter 2 2.8 Observations and Hypo
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Chapter 2 Literature concerning veh
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Chapter 2 philosophical concepts fo
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Chapter 3 3.1 EV Battery Systems In
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Chapter 3 The equivalent circuit lo
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Chapter 3 merits, some of these tec
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Chapter 3 where 1Ah = 3600C. The Ah
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Chapter 3 same state of charge. As
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Chapter 3 The state of discharge (S
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Chapter 3 provided by the battery m
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Chapter 3 Figure 3.5 illustrates an
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Chapter 3 where Voc[SoC] and Ri[SoC
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Chapter 3 Power(Watt) 4000 3500 300
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Chapter 3 Batt Voltage (V) Charging
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Chapter 3 Voc Voc Ri Ri R chg R chg
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Chapter 3 Description [Unit] Parame
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Chapter 3 3.17 Ultracapacitors Ultr
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Chapter 3 voltage on charge and a d
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Chapter 3 As with the battery model
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Chapter 3 The energy capacity, E of
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Chapter 3 3.20 Ultracapacitors in s
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Chapter 3 Voltage (V) Time (s) 92 p
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Chapter 3 3.21 Hybridisation of Bat
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Chapter 3 83.50 50.00 Current (A) 0
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Chapter 3 In section 3.11, it was s
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Chapter 4 4.1 Vehicle Longitudinal
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Chapter 4 where sgn[vxT] is a the s
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Chapter 4 P Load dP Load /dt > 0 P
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Chapter 4 braking energy. Regenerat
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Chapter 4 Angular Velocity (rad/s)
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Chapter 4 electrical terminal power
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Chapter 4 112 Type 1 -Energy Sytem
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Chapter 4 Battery Power (W) Profile
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Chapter 4 Energy (J) CASE 2 Battery
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Chapter 4 Battery Power (W) Profile
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Chapter 4 Energy (J) CASE 3 Battery
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Chapter 4 Energy (J) Energy (J) DIS
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Chapter 4 occur more frequently bef
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Chapter 5 CHAPTER 5 THE MANAGEMENT
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Chapter 5 Under the directives and
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Chapter 5 Hierarchy Mid-Level Low-L
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Chapter 5 While the breadth of the
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Chapter 5 The complete modular stru
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Chapter 5 conceive and implement. T
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Chapter 5 where, P req is the reque
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Chapter 5 Max Velocity Mode [Run,Id
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Chapter 5 decision epoch window (
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Chapter 5 P uc max Power 0 ∆PMS t
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Chapter 5 (W) (W) (W) Figure 5.11 L
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Chapter 5 An important difference w
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Chapter 5 IF x1 is Ai1 AND x2 is Ai
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Chapter 5 In this strategy, only P
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Page 247 and 248: References [15] R. H. Staunton, C.
Page 249 and 250: References [43] B. E. Conway, Elect
Page 251 and 252: References [73] A. Drolia, P. Jose,
Page 253 and 254: References [101] E. Surewaard, E. K
Page 255 and 256: Appendices Appendix A: Schematics A
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1 2 3 4 5 6 7 A ID L batt L UC K1 B
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1 2 3 4 5 6 7 A ID START STOP START
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1 2 3 4 5 6 7 A ID B C D E F G H I
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1 2 3 4 5 6 7 A ID START STOP START
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Minimum Duty Cycle Maximum Duty Cyc
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Type Test- 03 Type testing of the g
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Power, interfacing and sub control
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PhD Thesis - Cranfield University

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