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PhD Thesis - Cranfield University

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1<br />

2<br />

3<br />

4<br />

5<br />

6<br />

7<br />

A<br />

Enable<br />

Key switch<br />

ID<br />

B C D E F G H I J K<br />

4 core<br />

GRN<br />

Upper<br />

Limit<br />

to<br />

Pedal RED<br />

Lower<br />

1K<br />

YEL Limit<br />

4 core<br />

to<br />

Pedal<br />

<strong>PhD</strong> Project<br />

LCR<br />

RED<br />

BLU<br />

BLU<br />

BRN<br />

BLU<br />

BLK<br />

Spares<br />

RED<br />

BLU<br />

YEL<br />

WHT<br />

YEL<br />

BLK<br />

RED<br />

BLU<br />

GRN<br />

Spares<br />

4core<br />

to<br />

4QD<br />

6 core<br />

to<br />

4QD<br />

Marshalling board connection diagram<br />

2.2nF<br />

2.2nF<br />

2.2nF<br />

75K<br />

820K<br />

75K<br />

820K<br />

75K<br />

820K<br />

fo= 1/(2π.75k . 2.2n)<br />

= 964Hz<br />

Rev. Note: NIL<br />

File C:\<strong>PhD</strong>Project\Dwg\ELE-007<br />

REV -0<br />

+<br />

+<br />

+<br />

RED<br />

BLU<br />

RED<br />

BLU<br />

RED<br />

BLU<br />

1nF<br />

YEL<br />

WHT<br />

BLU<br />

GRN<br />

RED<br />

BLK<br />

CH2<br />

Ultracap<br />

CH1<br />

Batt<br />

CH0<br />

DC Bus<br />

Drawn<br />

CHK<br />

APV<br />

12V<br />

Incoming<br />

CRANFIELD UNIVERSITY<br />

LCR<br />

12V<br />

to<br />

CFP<br />

6core to<br />

CFP<br />

Slot 01<br />

02-05-2006<br />

Drawing No: ELE-007<br />

Sheet<br />

1/1

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