course contents - ug - National Institute of Technology Karnataka
course contents - ug - National Institute of Technology Karnataka
course contents - ug - National Institute of Technology Karnataka
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NATIONAL INSTITUTE OF TECHNOLOGY KARNATAKA, SURATHAKAL<br />
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Testing <strong>of</strong> rubber mats. Testing <strong>of</strong> Gas Insulated Substations. There will be few typical experiments<br />
based on the <strong>course</strong> content.<br />
Kamaraju, Naidu, High Voltage Engineering.<br />
Kuffel, Zeangle, High Voltage Engineering.<br />
Relevant Indian standards and Technical papers.<br />
EE476 OPTIMISATION TECHNIQUES (3-0-0) 3<br />
Linear Programming: Simplex method and extensions. Network models: Shortest path, maximum flow<br />
and minimum cost problems. Dynamic programming: resource allocation, production scheduling and<br />
equipment replacement problem. Non-linear programming: selected unconstrained and constrained nonlinear<br />
programming algorithms like quasi Newton, reduced gradient and gradient projection methods.<br />
Penalty function methods, Quadratic programming.<br />
Lueneburger , Linear and Non linear Programming, McGraw-Hill.<br />
Fletcher, Optimization techniques, John Wiley and Sons.<br />
EE478 AN INTRODUCTION TO THE INTEL IA-32 ARCHITECTURE (3-1-0) 4<br />
A brief history <strong>of</strong> the IA-32 architecture, the Intel P6 family <strong>of</strong> processors � Intel Pentium®, Xeon®,<br />
Pentium® M, Pentium® Extreme, Core� Duo and Core� Solo. SIMD instructions, Hyper-threading<br />
technology, Multicore technology. Basic execution environment, Memory Organization, Paging and<br />
Virtual memory, Address calculations in 64-bit mode. basic program execution registers, Instruction<br />
pointer, Operand addressing, memory operands, segmentation, I/O port addressing. Data types: numeric,<br />
pointer, bit-field, string, packed-SIMD, BCD. Implementation <strong>of</strong> the IEEE 754 floating point format.<br />
Overview <strong>of</strong> FP exceptions and FP exception handling.<br />
Instruction set summary � General purpose instructions, FPU instructions, MMX instructions, SSE<br />
instructions, SSE2 and SSE3 extensions. Programming with GP instructions, Programming with<br />
the x87 FPU. Instruction prefixes, encoding, displacement. Interrupts and exception handling.<br />
Programming the IA-32 in the GNU/Linux environment.<br />
Intel Corporation, IA-32 Intel Architecture S<strong>of</strong>tware Developer's Manual, Volume1:Basic Architecture,<br />
Intel Corporation, 2006.<br />
Intel Corporation, IA-32 Intel Architecture S<strong>of</strong>tware Developer's Manual, Volume 2A: Instruction Set<br />
Reference, A-M, Intel Corporation, 2006.<br />
Intel Corporation, IA-32 Intel Architecture S<strong>of</strong>tware Developer's Manual, Volume 2B: Instruction Set<br />
Reference, N-Z, Intel Corporation, 2006.<br />
Intel Corporation, IA-32 Intel Architecture Optimization Reference Manual, Intel Corporation, 2006.<br />
http://developer.intel.com/design/<br />
http://www.intel.com/design/archives/<br />
http://www.x86.org/intel.doc/<br />
EE489 ADVANCED ELECTRIC DRIVES LAB (0-0-3) 2<br />
Laboratory exercises and assignments to provide additional support to EE468.<br />
EE490 SEMINAR (0-0-2) 1<br />
This <strong>course</strong> is a 1 credit <strong>course</strong> to be completed during 7 th / 8 th semester. The student will make<br />
presentations on topics <strong>of</strong> academic interest.<br />
EE491 INSULATION AND TESTING ENGINEERING LAB LAB (0-0-3) 2<br />
Laboratory exercises and assignments to provide additional support to EE472.<br />
EE499 MAJOR PROJECT-II (0-1-6) 5<br />
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