SMSC LPC47N252 Data Sheet - Keil

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1.1 REFERENCE DOCUMENTS 1.1.1 INTEL LOW PIN COUNT SPECIFICATION Revision 1.0, September 29, 1997. 1.1.2 PCI LOCAL BUS SPECIFICATION Revision 2.2, December 18, 1998 1.1.3 ADVANCED CONFIGURATION AND POWER INTERFACE SPECIFICATION Revision 1.0a, July 1, 1998 1.1.4 LPC47N252 NOTEBOOK I/O CONTROLLER WITH ENHANCED KEYBOARD CONTROL AND SYSTEM MANAGEMENT SMSC Data Sheet, Revision 6/8/99 1.1.5 IEEE 1284 EXTENDED CAPABILITIES PORT PROTOCOL AND ISA INTERFACE STANDARD Rev 1.14, July 14, 1993. This document is available from Microsoft. SMSC DS – LPC47N252 Page 12 Rev. 09/06/2000
SMSC DS – LPC47N252 Page 13 Rev. 09/06/2000 2 TQFP PIN CONFIGURATION 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 GPIO19 SGPIO40 GPIO17 VCC1 GPIO16 OUT7 OUT8 OUT9 OUT10 OUT11 nFDD_LED nBAT_LED AB1A_CLK AB1A_DATA OUT5 nEA VSS GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 VSS nFWP TEST_PIN VCC2 nDMS_LED FDC_nPP AB1B_CLK VCC1 AB1B_DATA LGPIO77 LGPIO76 LGPIO75 LGPIO74 LGPIO73 LGPIO72 LGPIO71 VSS LGPIO70 LGPIO67 LGPIO66 LGPIO65 VCC 1 PGM AGND XTAL2 XTAL1 XOSEL MODE OUT6 VCC2 DRVDEN0 DRVDEN1 nMTR0 VSS nDS0 nDIR nSTEP nWDATA nWGATE nHDSEL nINDEX nTRK0 nWRTPRT nRDATA nDSKCHG FPD IRTX IRRX KSO13 KSO12 KSO11 KSO10 KSO9 KSO8 KSO7 VCC1 KSO6 KSO5 KSO4 KSO3 KSO2 KSO1 KSO0 KSI7 KSI6 KSI5 KSI4 KSI3 KSI2 KSI1 KSI0 GPIO20 GPIO21 IMCLK IMDAT VSS KCLK KDAT EMCLK EMDAT SGPIO30 SGPIO31 SGPIO32 SGPIO33 SGPIO34 SGPIO35 SGPIO36 SGPIO37 VCC1 SGPIO41 SGPIO42 SGPIO43 SGPIO44 SGPIO45 SGPIO46 SGPIO47 OUT0 OUT1 OUT2 VSS OUT3 OUT4 LGPIO50 LGPIO51 LGPIO52 LGPIO53 LGPIO54 LGPIO55 LGPIO56 VCC1 LGPIO57 LGPIO60 LGPIO61 LGPIO62 LGPIO63 VSS LGPIO64 LPCPD# LAD[0] LAD[1] LAD[2] LAD[3] LDRQ# LFRAME# LRESET# PCI_CLK nCLKRUN SER_IRQ nRESET_OUT CLOCKI VCC2 VCC0 IN7 IN6 IN5 IN4 IN3 IN2 IN1 IN0 GPIO12 GPIO11 GPIO10 GPIO13 VCC1 GPIO9 GPIO8 GPIO14 GPIO15 nRI nDCD nDTR nCTS nRTS nDSR VSS TXD RXD nSTROBE nALF nERROR nINIT nSLCTIN PD0 PD1 PD2 PD3 VCC2 PD4 PD5 PD6 PD7 nACK BUSY PE SLCT PWRGD nPWR_LED VCC1_PWRGD 32kHz_OUT VSS nEC_SCI 24MHz_OUT LPC47N252 208 PIN TQFP FIGURE 1 - LPC47N252 PIN CONFIGURATION Note: For FBGA BALL PAD Configuration see FIGURE 102 - 208 PIN FLEX BGA 15.0X15.0X1.10 ( PR ELIMIN AR Y) .
Page 1 and 2: _ Advanced Notebook I/O Controller
Page 3 and 4: GENERAL DESCRIPTION The LPC47N252 i
Page 5 and 6: 5.7.1 Read Data....................
Page 7 and 8: 12.2 FLASH MEMORY ARRAY ...........
Page 9 and 10: 21.1 FAN TACHOMETER OVERVIEW ......
Page 11: APPENDIX A: HIGH-PERFORMANCE 8051 C
Page 15 and 16: 3 PIN FUNCTIONS TQFP PIN # FBGA NAM
Page 17 and 18: TQFP PIN NOTES NAME DESCRIPTION 44:
Page 19 and 20: TQFP PIN NOTES NAME DESCRIPTION 166
Page 21 and 22: Note 8: OUT0 and GPIO7 are suitable
Page 23 and 24: DEFAULT FUNCTION PWR ALTERNATE FUNC
Page 25 and 26: 4 FUNCTIONAL DESCRIPTION The host p
Page 27 and 28: Table 6 - Basic Lpc Bus Cycle Descr
Page 29 and 30: 4.1.7.1 DMA Acknowledge The DMA ack
Page 31 and 32: 4.1.8.4 Sync Error Indication The p
Page 33 and 34: FIELD DRIVEN BY CLOCKS LAD[3:0] COM
Page 35 and 36: FIELD DRIVEN BY CLOCKS LAD[3:0] COM
Page 37 and 38: state (ACPI S1, APM POS), LPCPD# ma
Page 39 and 40: BIT 4 nTRACK 0 Active low status of
Page 41 and 42: BIT 3 READ DATA Active high status
Page 43 and 44: Enhanced Floppy Mode 2 (OS2) TAPE S
Page 45 and 46: 10 = 2 Meg Tape Note 1: The DRATE a
Page 47 and 48: BIT 0 - 6 UNDEFINED The data bus ou
Page 49 and 50: Table 41 - FDC Status Register 0 B
Page 51 and 52: DOR Reset vs. DSR Reset (Software R
Page 53 and 54: RQM and DIO must both equal "1" bef
Page 55 and 56: 5.6 FDC INSTRUCTION SET Table 46 -
Page 57 and 58: R EA D A T RA C K D AT A B US PHA S
Page 59 and 60: SPECIF Y D AT A B US PHA SE R /W D
Page 61 and 62: INVAL ID COD ES D AT A B US PHA SE
Page 63 and 64:
SK BIT VAL UE 5.7.3 READ A TRACK Ta
Page 65 and 66:
Table 52 - Verify Command Result Ph
Page 67 and 68:
5.8 FDC CONTROL COMMANDS Control co
Page 69 and 70:
0 1 .. E F 00 01 02 .. 7F 7F Table
Page 71 and 72:
Gap2 field is expanded to a length
Page 73 and 74:
MECHANISM FDC OUTPUT PINS STATE FDC
Page 75 and 76:
6 ACPI EMBEDDED CONTROLLER ACPI def
Page 77 and 78:
Once the host reads the data, the O
Page 79 and 80:
7 SERIAL PORT (UART) The LPC47N252
Page 81 and 82:
7.1.5 INTERRUPT IDENTIFICATION REGI
Page 83 and 84:
Table 67 - Serial Character B IT 1
Page 85 and 86:
BIT 3 Framing Error (FE). Bit 3 ind
Page 87 and 88:
D ESIR ED B AU D R AT E D IVISOR US
Page 89 and 90:
7.3.1 EFFECT OF THE RESET ON REGIST
Page 91 and 92:
and the CPU starts to load it. When
Page 93 and 94:
8.1 IRRX/IRTX PIN ENABLE When MISC2
Page 95 and 96:
9 PARALLEL PORT The LPC47N252 incor
Page 97 and 98:
BITS 1, 2 are not implemented as re
Page 99 and 100:
9.1.1.9.2 EPP 1.9 Write The timing
Page 101 and 102:
The chip drives the final sync and
Page 103 and 104:
The bit map of the Extended Paralle
Page 105 and 106:
Table 83 - Extended Control Registe
Page 107 and 108:
9.2.4.7 ister A) - ADDRESS OFFSET =
Page 109 and 110:
9.2.5.2 ECP Operation Prior to ECP
Page 111 and 112:
to 0. The ECP requests DMA transfer
Page 113 and 114:
9.3.3.1 PPPI FDC pin out The FDC si
Page 115 and 116:
Table 90 - FDC_nPP Initiated Pppi M
Page 117 and 118:
Accessing the LPC47N252 during powe
Page 119 and 120:
10.8 UART POWER MANAGEMENT Direct p
Page 121 and 122:
11.2.1 FUNCTIONAL BLOCKS Below are
Page 123 and 124:
System is running (Vcc2 and Vcc1 ar
Page 125 and 126:
KBDCLK[1:0] These 2 bits control th
Page 127 and 128:
FIX BIT REGISTERS SFR REGISTER NAME
Page 129 and 130:
MMCR REGISTER NAME SYSTEM ADDRESS S
Page 131 and 132:
MMCR REGISTER NAME SYSTEM ADDRESS S
Page 133 and 134:
11.8.3.3 Device ID Register By read
Page 135 and 136:
11.8.3.6 8051 LPC Bus Monitor The 8
Page 137 and 138:
IN4 IN5 GPIO0 GPIO1 GPIO2 IN6 GPIO7
Page 139 and 140:
11.9.3 8051 INT0 MASK REGISTER Tabl
Page 141 and 142:
RTC_ALRM asserted [D0] The RTC_ALRM
Page 143 and 144:
Table 118 - Wakeup Source Register
Page 145 and 146:
Table 125 - Wakeup Mask Register 7
Page 147 and 148:
Table 132 - Edge Select 5B HOST ADD
Page 149 and 150:
8051_IRQ ENABLE 8051_IRQ SELECT DES
Page 151 and 152:
12 64K EMBEDDED FLASH ROM 12.1 OVER
Page 153 and 154:
12.3 COMMAND SEQUENCE INTERFACE (CS
Page 155 and 156:
CMD CODE (hex) CSI MODE DESCRIPTION
Page 157 and 158:
12.3.6.1 Busy Bit - D7 The BUSY ind
Page 159 and 160:
12.3.7.2 Read Array Mode READ ARRAY
Page 161 and 162:
12.3.7.4 Page Erase Mode In Page Er
Page 163 and 164:
The CSI host interface and the Flas
Page 165 and 166:
Table 151 - 8051 Flash Boot Block P
Page 167 and 168:
Declarations ERROR_MASK = 0x0070; /
Page 169 and 170:
13 FLASH PROGRAMMING INTERFACE 13.1
Page 171 and 172:
FLASH PROGRAM REGISTER EXT FLASH (D
Page 173 and 174:
FPA[15:8] FPALE FPAD[7:0] nFPRD nFP
Page 175 and 176:
test vector FPA15:8 FPAD7:0 FPALE n
Page 177 and 178:
EFALE nEFRD EFAD[7:0] EFA[15:8] t1
Page 179 and 180:
13.9 DEADMAN SWITCH 13.9.1 OVERVIEW
Page 181 and 182:
13.9.4 DMS REGISTER T P FIGURE 42 -
Page 183 and 184:
13.10.3 EXT FLASH - D3 The EXT FLAS
Page 185 and 186:
13.12 INTERNAL SCRATCH ROM The Kahu
Page 187 and 188:
14.5 WDT MEMORY MAPPED REGISTERS Ta
Page 189 and 190:
15.1.1 EXITING IDLE MODE FIGURE 46
Page 191 and 192:
15.3 WAKE-UP EVENTS N 8051 in sleep
Page 193 and 194:
PIN WAKE-UP EVENTS GPIO11 WK_SE15 W
Page 195 and 196:
16 KEYBOARD CONTROLLER 16.1 8042 ST
Page 197 and 198:
Table 177 - PCOBF HOST N/A 8051 0x7
Page 199 and 200:
SA2 R/W D[0:7] IBF FLAG GATEA20 COM
Page 201 and 202:
FE Command From KRESET Speed up Log
Page 203 and 204:
16.6 DIRECT KEYBOARD SCAN The LPC47
Page 205 and 206:
6) When the controller is ready to
Page 207 and 208:
PS2_T/R PS/2 Channel Transmit/Recei
Page 209 and 210:
If the time from the 1st (start) bi
Page 211 and 212:
When sending a byte to a DEVIL PS/2
Page 213 and 214:
17.6.2 DEVIL PS/2 STATUS REGISTERS
Page 215 and 216:
17.6.5 DEVIL PS/2 RECEIVE REGISTERS
Page 217 and 218:
Table 195 - ACCESS.Bus Register Add
Page 219 and 220:
BIT 7 - PIN Pending Interrupt Not.
Page 221 and 222:
18.2.5 CLOCK REGISTER The Clock Reg
Page 223 and 224:
19 MAILBOX REGISTER INTERFACE 19.1
Page 225 and 226:
19.5 THE SYSTEM/8051 INTERFACE REGI
Page 227 and 228:
System is fully powered & the 8051i
Page 229 and 230:
19.8 FDC SHADOW REGISTERS The LPC47
Page 231 and 232:
20 PULSE WIDTH MODULATORS 20.1 OVER
Page 233 and 234:
MAILBOX INDEX Table 218 - PWM1 Spee
Page 235 and 236:
PWM0 Clock Multiplier, D2 The PWM0
Page 237 and 238:
FAN1 and FAN2 Read Latch registers
Page 239 and 240:
21.5 FAN2 READ LATCH REGISTER The F
Page 241 and 242:
22 8051 CONTROLLED PARALLEL PORT To
Page 243 and 244:
23 HOST CONTROLLED IR PORT It is po
Page 245 and 246:
ITEM TYPE PIN NAMES WAKE CAPABLE BU
Page 247 and 248:
Table 230 - GPIO Input Register A H
Page 249 and 250:
Table 238 -Out Register D HOST ADDR
Page 251 and 252:
24.4.1 LPC LGPIO BASE ADDRESS Logic
Page 253 and 254:
Table 247 - LPC LGPIO Direction Reg
Page 255 and 256:
8051 MMCR ADDRESS REGISTER TYPE 805
Page 257 and 258:
24.4.3.3 8051 LGPIO Group I Registe
Page 259 and 260:
Table 266 - GPIO Buffer Type Config
Page 261 and 262:
24.6 GPIO PASS-THROUGH PORTS The LP
Page 263 and 264:
25 MULTIFUNCTION PIN 25.1 OVERVIEW
Page 265 and 266:
MISC[3,1] - D3 and D1 The MISC3 bit
Page 267 and 268:
Table 286 - Misc14 And Misc13 Bits
Page 269 and 270:
driven open-drain, and the Serial I
Page 271 and 272:
Block base address must be located
Page 273 and 274:
26.5.4 POWER MANAGEMENT 1 ENABLE RE
Page 275 and 276:
27 REAL TIME CLOCK 27.1 GENERAL DES
Page 277 and 278:
The 12/24 bit in Register B establi
Page 279 and 280:
27.7.2 REGISTER B RATE SELECT 32.76
Page 281 and 282:
27.7.6 GENERAL PURPOSE Registers 0x
Page 283 and 284:
27.10 32KHZ CLOCK INPUT The LPC47N2
Page 285 and 286:
Note 1 : “Change” means either-
Page 287 and 288:
1) Quiet (Active) Mode Any device m
Page 289 and 290:
30 XNOR-CHAIN TEST MODE An XNOR-Cha
Page 291 and 292:
31.2.2 CONFIGURATION SEQUENCE EXAMP
Page 293 and 294:
HARD SOFT INDEX TYPE RESET RESET CO
Page 295 and 296:
REGISTER ADDRESS DESCRIPTION PowerC
Page 297 and 298:
LOGICAL DEVICE REGISTER ADDRESS DES
Page 299 and 300:
LOGICAL DEVICE NUMBER LOGICAL DEVIC
Page 301 and 302:
31.9.4 PARALLEL PORT SPP and EPP mo
Page 303 and 304:
NAME REG INDEX DEFINITION FDD0 0xF4
Page 305 and 306:
NAME IR Half Duplex Timeout Default
Page 307 and 308:
PAR AM ETER SYM BOL M IN T YP M AX
Page 309 and 310:
PAR AM ETER IOD 16 Type Bu ff er SY
Page 311 and 312:
32.3 AC SPECIFICATIONS AC Test Cond
Page 313 and 314:
33.2 LPC TIMING CLK Output Delay Tr
Page 315 and 316:
33.3 FLOPPY DISK TIMING nDIR nSTEP
Page 317 and 318:
nWRITE PD nDATASTB nADDRSTB nWAIT t
Page 319 and 320:
33.5 ECP PARALLEL PORT TIMING Paral
Page 321 and 322:
nALF PD nSTROBE BUSY t2 t1 t7 t8 t6
Page 323 and 324:
33.6 SER IA L IRQ TIMIN G PCI_CLK S
Page 325 and 326:
33.9 FAN AND FAN TACHOMETER TIMING
Page 327 and 328:
PS2_CLK PS2_DAT PS2_EN PS2_T/R XMIT
Page 329 and 330:
33.11 FLASH TIMING EFALE nEFRD EFAD
Page 331 and 332:
FIGURE 102 - 208 PIN FL EX BGA 15.0
Page 333 and 334:
INSTRUCTION DESCRIPTION BYTE COUNT
Page 335 and 336:
INSTRUCTION DESCRIPTION BYTE COUNT
Page 337 and 338:
The LPC47N252 adds a second data po
Page 339 and 340:
Table 333 - CKCON Register - SFR 8E
Page 341 and 342:
TL2 The TL2 register (Table 340) is
Page 343 and 344:
Table 345 - Eicon Register Bit Desc
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SMSC LPC47N252 Data Sheet - Keil

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