SMSC LPC47N252 Data Sheet - Keil

4.1.4 ABORT MECHANISM
The host can use LFRAME# to force a peripheral off the LPC Bus. See the Intel Low Pin Count Specification,
Section 4.2.2.2, for timing for the abort mechanism using LFRAME#.
Note: The LPC47N252 adheres to the following abort policy: on target I/O and DMA cycles, if the host signals an
abort before the peripheral has asserted the ‘ready’ or ‘error’ SYNC, the cycle will be terminated. No data is to be
transferred to the host on I/O reads or DMA writes, and the data written to the LPC47N252 on I/O writes and DMA
reads is to be ignored. Note that once the LPC47N252 asserts the ready SYNC, the host will not abort.
4.1.5 I/O READ AND WRITE CYCLES
I/O cycles are initiated by the host for register or FIFO accesses and will generally have minimal Sync times. The
minimum number of wait-states between bytes is 1. EPP cycles will depend on the speed of the external device, and
may have much longer Sync times.
Data transfers are assumed to be exactly 1-byte. If the CPU requested a 16 or 32-bit transfer, the host will break it
up into 8-bit transfers.
4.1.6 DMA READ AND WRITE CYCLES
DMA read cycles involve the transfer of data from the host (main memory) to the peripheral. DMA write cycles
involve the transfer of data from the peripheral to the host (main memory). Data will be coming from or going to a
FIFO and will have minimal Sync times. DMA data transfers to/from The LPC47N252 are single bytes.
4.1.7 DMA REQUEST
To initiate DMA service, the peripheral encodes its requested channel number on the LDRQ# signal. Each peripheral
has its own dedicated LDRQ# signal.
LDRQ# is synchronous with the PCI clock (see section 28.2.2, nCLKRUN Support for LPC DMA Cycle on page 284).
The peripheral starts the DMA cycle by asserting a START bit. The START bit is LDRQ# asserted (low) for one PCI
clock cycle (FIGURE 6). The next three bits contain the encoded requested DMA channel number (MSB first).
The ACT bit follows the LSB bit. The ACT bit indicates if the encoding is associated with the DMA request going
active or inactive; i.e., ACT = ‘1’ if the request is active, ACT = ‘0’ if the request is inactive. The ACT bit allows for a
previous DMA request for that channel to be abandoned (see Intel Low Pin Count Specification, Section 6.3). Note:
The LPC47N252 implements support for the ACT bit.
Following the ACT bit, the peripheral must deassert the LDRQ# signal (high) for at least 1 clock. After that, the
LDRQ# signal can be brought back low to start the next encoding (for another channel).
Peripherals do not have to wait for the CHANNEL field to deassert LDRQ# to begin encoding for another channel.
This allows additional DMA requests to be indicated, even if the first one has not yet been acknowledged.
Using the LDRQ# encoding to request a transfer for a particular channel should not be attempted if one is still
pending for that channel. Therefore, to encode another LDRQ# for the same channel, the part must wait 8 LCLKs
after it sends a SYNC encoding of 0000 for that channel. However, using a SYNC value of 1001 replaces the
LDRQ# encoding for the same channel. Therefore, the only time that it is necessary to send another LDRQ# is if a
SYNC of 0000 is used.
To attempt to abandon a previously requested DMA transfer, the peripheral sends an encoding on LDRQ# for that
channel, but with the ACT bit set to 0 (see the Intel Low Pin Count Specification, Section 6.3 for a description of
abandoning DMA requests).
LCLK
LDRQ#
Start MSB LSB ACT Start
FIGURE 6 - LDRQ# ENCODING
SMSC DS – LPC47N252 Page 28 Rev. 09/06/2000