SMSC LPC47N252 Data Sheet - Keil

FIELD DRIVEN BY CLOCKS LAD[3:0] COMMENT
TAR Host 1 1111 Host drives LAD[3:0] high in 1st half
TAR Special 1 1111 Not driven
Sync Peripheral 1 1001 Sync=1001 (more transfers req’d)
Data Peripheral 1 xxxx First nibble of first byte of first word
Data Peripheral 1 xxxx Second nibble of first byte of first word
Sync Peripheral 1 1001 Sync=1001 (more transfers req’d)
Data Peripheral 1 xxxx First nibble of second byte of first word
Data Peripheral 1 xxxx Second nibble of second byte of first word
TAR Peripheral 1 1111 Peripheral drives LAD[3:0] high in 1st half
TAR Special 1 1111 Not driven
The cycles below may not immediately follow. (Note 4)
START Host 1 0000 LAD[3:0]=0000 - Second Word -
CYCTYP+DIR Host 1 101x LAD[3:2]=10 (DMA), LAD[1]=1 (write)
CHANNEL Host 1 0xxx LAD[3]=0, LAD[2:0] = Ch # (acts as DMA Ack)
SIZE Host 1 xx01 LAD[1:0]=01 (16-bit)
TAR Host 1 1111 Host drives LAD[3:0] high in 1st half
TAR Special 1 1111 Not driven
Sync Peripheral 1 1001 Sync=1001 (more transfers req’d)
Data Peripheral 1 xxxx First nibble of first byte of second word
Data Peripheral 1 xxxx Second nibble of first byte of second word
Sync Peripheral 1 1001 Sync=1001 (more transfers req’d)
Data Peripheral 1 xxxx First nibble of second byte of second word
Data Peripheral 1 xxxx Second nibble of second byte of second word
TAR Peripheral 1 1111 Peripheral drives LAD[3:0] high in 1st half
TAR Special 1 1111 Not driven
The cycles below may not immediately follow. (Note 4)
START Host 1 0000 LAD[3:0]=0000 - Third Word -
CYCTYP+DIR Host 1 1000 LAD[3:2]=10 (DMA), LAD[1]=1 (write)
CHANNEL Host 1 1xxx LAD[3]=1 = TC (second byte transferred is the last
one) LAD[2:0] = Ch #
SIZE Host 1 xx01 LAD[1:0]=01 (16-bit)
TAR Host 1 1111 Host drives LAD[3:0] high in 1st half
TAR Special 1 1111 Not driven
Sync Peripheral 1 1001 Sync=1001 (more transfers req’d)
Data Peripheral 1 xxxx First nibble of first byte of third word
Data Peripheral 1 xxxx Second nibble of first byte of third word
Sync Peripheral 1 0000 Sync=0000 (no more transfers req’d)
Data Peripheral 1 xxxx First nibble of second byte of third word
Data Peripheral 1 xxxx Second nibble of second byte of third word
TAR Peripheral 1 1111 Peripheral drives LAD[3:0] high in 1st half
TAR Special 1 1111 Not driven
Note 4: These DMA cycles can be interspersed with I/O cycles, memory cycles or other DMA cycles.
4.1.14 LPC POWER MANAGEMENT
The LPCPD# signal (see the Intel Low Pin Count Specification, Section 8.1) and the nCLKRUN signal (see the Intel
Low Pin Count Specification, Section 8.2) are implemented in the LPC47N252. The LPC47N252 must tolerate the
LPCPD# signal going active and then inactive again without LRESET# going active. This is a requirement for
notebook power management functions.
The LPC Bus spec 1.0 section 8.2 states that "After LPCPD# goes back inactive, the LPC I/F will always be reset
using LRST#”. This text must be qualified for mobile systems where it is possible that when exiting a "light" sleep
SMSC DS – LPC47N252 Page 36 Rev. 09/06/2000