SMSC LPC47N252 Data Sheet - Keil

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3.1.1 ALTERNATE FUNCTION PINS BUFFER SYMBOL DESCRIPTION PCI_ICLK PCI clock input PCI_IO PCI bidirectional PCI_O PCI ouput PCI_OD PCI open drain ICLK Clock input ICLK2 Clock input 2 OCLK2 Clock output 2 O24 Output – 12mA, 6mA source Many of the LPC47N252’s signal pins provide alternate functions which may be enabled by the 8051 firmware based on the system design requirements: The pins are identified by primary pin function (Note that some functions are available on more than one pin; e.g., OUT8 and KBRST. DEFAULT FUNCTION PWR ALTERNATE Table 4 - Alternate Function Pins ALTERNATE MULTIPLEX CONTROLS FUNCTION #1 PWR FUNCTION #2 PWR BIT NOTES OUT1 VCC1 nIRQ8 VCC2 - - MISC0 Note 20 OUT5 VCC1 nDS1 VCC2 KBRST VCC2 MISC[5, 22] Note 20 Note 22 OUT6 VCC1 nMTR1 VCC2 - - MISC5 Note 20 OUT7 VCC1 nSMI VCC2 - - MISC18 Note 20 OUT8 VCC1 KBRST VCC2 MISC[17, 6] Note 20 OUT9 VCC1 PWM2 VCC1 - - MISC11 OUT10 VCC1 PWM0 VCC1 - - MISC4 OUT11 VCC1 PWM1 VCC1 - - MISC12 GPIO4 VCC1 KSO14 VCC1 - - GPIO5 VCC1 KSO15 VCC1 - - MISC9 GPIO6 VCC1 IRMODE/IRRX3A VCC2 - - MISC[14, 13] Note 20 GPIO8 VCC1 IRRX2 VCC1 - - GPIO9 VCC1 IRTX2 VCC2 - - MISC[7, 2] GPIO10 VCC1 IRMODE/IRRX3B VCC2 - - MISC[16, 15] GPIO11 VCC1 AB2A_DATA VCC1 GPIO12 VCC1 AB2A_CLK VCC1 GPIO13 VCC1 AB2B_DATA VCC1 GPIO14 VCC1 AB2B_CLK VCC1 MISC[20, 19] Note 21 GPIO15 VCC1 FAN_TACH1 VCC1 MISC23 MISC23 GPIO16 VCC1 FAN_TACH2 VCC1 MISC21 MISC21 GPIO17 VCC1 A20M VCC1 - - MISC6 Note 20 GPIO20 VCC1 PS2CLK VCC2 8051RX VCC1 MISC[3, 1] Note 20 GPIO21 VCC1 PS2DAT VCC2 8051TX VCC1 Note 20 KSO12 VCC1 OUT8 VCC1 KBRST VCC2 MISC[17, 6] Note 20 KSO13 VCC1 GPIO18 VCC1 MISC[17] nINIT VCC2 nDIR VCC2 - - nSLCTIN VCC2 nSTEP VCC2 - - PD0 VCC2 nINDEX VCC2 - - PD1 VCC2 nTRK0 VCC2 - - PD2 VCC2 nWRTPRT VCC2 - - PD3 VCC2 nRDATA VCC2 - - PD4 VCC2 nDSKCHG VCC2 - - PD6 VCC2 nMTR0 VCC2 - - SLCT VCC2 nWGATE VCC2 - - CR2 5[ 4 :3 ] SMSC DS – LPC47N252 Page 22 Rev. 09/06/2000
DEFAULT FUNCTION PWR ALTERNATE FUNCTION #1 PWR PE VCC2 nWDATA VCC2 - - BUSY VCC2 nMTR1 VCC2 - - nACK VCC2 nDS1 VCC2 - - nERROR VCC2 nHDSEL VCC2 - - nALF VCC2 DRVDEN0 VCC2 - - nSTROBE VCC2 nDS0 VCC2 - - Note 19:See a description in the MULTIFUNCTION PIN section 25. ALTERNATE MULTIPLEX CONTROLS FUNCTION #2 PWR BIT NOTES Note 20: When this pin is configured as a VCC2 powered alternate function output and PWRGD is inactive (i.e. VCC2 is 0v), the pin will tri-state to prevent back-biasing of external circuitry (see Section 24.) Note 21:This pin defaults to “output”, “low” for both the default (GPIO) function and the alternate (IRTX) function, regardless of the state of PWRGD to prevent infrared transceiver damage (see MISC[7, 2] bits of the Multiplexing_1 Register – MISC (7:0) Note 22: MISC5 must be inactive for MISC22 to enable KBRST. 3.2 POWER CONFIGURATION There are three power planes in the LPC47N252 VCC0, VCC1, and VCC2 with the following power sequencing requirement: VCC2 shall have power applied simultaneously with or after VCC1. VCC1 shall have power applied simultaneously with or after VCC0. VCC2 – VCC1 ≤ 0.5V All internal components which utilize VCC0 power plane are switched internally between the VCC1 and VCC0 pins according to VCC1_PWRGD. See FIGURE 4 - VCC2 POWER-UP TIMING and FIGURE 5 - VCC1_PWRGD TIMING. See Table 325 for power consumption in various states. Two LPC47N252 power supply configurations can be utilized. These power supply configuration types fundamentally differ upon the need for a backup battery (VBAT) connection to VCC0. TYPE 1 devices do not require a VCC0 battery connection. Power supply requirements for TYPE 1 devices are as follows: VCC0 is tied to VSS, VCC1 is connected to the main battery supply, and VCC2 is switched from either the main battery or AC power if available. In this configuration all internal components which utilize VCC0 power plane are switched internally to the VCC1 upon POR according to VCC1_PWRGD. TYPE 2 devices require a VCC0 battery connection. Power supply requirements for TYPE 2 devices are as follows: VCC0 is connected to a backup battery (V BAT), VCC1 is connected to the main battery supply, and VCC2 is switched from either the main battery or AC power if available. In this configuration all internal components which utilize VCC0 power plane only when VCC1 is absent. Normally (when VCC1_PWRGD is asserted) they are switched internally to the VCC1 power plane. The LPC47N252 provides unpredicted VCC2 power failures (See section 11.6, 8051 RING OSCILLATOR FAIL- SAFE CONTROLS on page 125.) PWRGD and VCC1_PWRGD timing is illustrated in FIGURE 3 through FIGURE 5. PWRGD VCC2 CLOCKI 10µs min. SMSC DS – LPC47N252 Page 23 Rev. 09/06/2000 3V FIGURE 3 – POWER-FAIL EVENT
Page 1 and 2: _ Advanced Notebook I/O Controller
Page 3 and 4: GENERAL DESCRIPTION The LPC47N252 i
Page 5 and 6: 5.7.1 Read Data....................
Page 7 and 8: 12.2 FLASH MEMORY ARRAY ...........
Page 9 and 10: 21.1 FAN TACHOMETER OVERVIEW ......
Page 11 and 12: APPENDIX A: HIGH-PERFORMANCE 8051 C
Page 13 and 14: SMSC DS - LPC47N252 Page 13 Rev. 09
Page 15 and 16: 3 PIN FUNCTIONS TQFP PIN # FBGA NAM
Page 17 and 18: TQFP PIN NOTES NAME DESCRIPTION 44:
Page 19 and 20: TQFP PIN NOTES NAME DESCRIPTION 166
Page 21: Note 8: OUT0 and GPIO7 are suitable
Page 25 and 26: 4 FUNCTIONAL DESCRIPTION The host p
Page 27 and 28: Table 6 - Basic Lpc Bus Cycle Descr
Page 29 and 30: 4.1.7.1 DMA Acknowledge The DMA ack
Page 31 and 32: 4.1.8.4 Sync Error Indication The p
Page 33 and 34: FIELD DRIVEN BY CLOCKS LAD[3:0] COM
Page 35 and 36: FIELD DRIVEN BY CLOCKS LAD[3:0] COM
Page 37 and 38: state (ACPI S1, APM POS), LPCPD# ma
Page 39 and 40: BIT 4 nTRACK 0 Active low status of
Page 41 and 42: BIT 3 READ DATA Active high status
Page 43 and 44: Enhanced Floppy Mode 2 (OS2) TAPE S
Page 45 and 46: 10 = 2 Meg Tape Note 1: The DRATE a
Page 47 and 48: BIT 0 - 6 UNDEFINED The data bus ou
Page 49 and 50: Table 41 - FDC Status Register 0 B
Page 51 and 52: DOR Reset vs. DSR Reset (Software R
Page 53 and 54: RQM and DIO must both equal "1" bef
Page 55 and 56: 5.6 FDC INSTRUCTION SET Table 46 -
Page 57 and 58: R EA D A T RA C K D AT A B US PHA S
Page 59 and 60: SPECIF Y D AT A B US PHA SE R /W D
Page 61 and 62: INVAL ID COD ES D AT A B US PHA SE
Page 63 and 64: SK BIT VAL UE 5.7.3 READ A TRACK Ta
Page 65 and 66: Table 52 - Verify Command Result Ph
Page 67 and 68: 5.8 FDC CONTROL COMMANDS Control co
Page 69 and 70: 0 1 .. E F 00 01 02 .. 7F 7F Table
Page 71 and 72: Gap2 field is expanded to a length
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MECHANISM FDC OUTPUT PINS STATE FDC
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6 ACPI EMBEDDED CONTROLLER ACPI def
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Once the host reads the data, the O
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7 SERIAL PORT (UART) The LPC47N252
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7.1.5 INTERRUPT IDENTIFICATION REGI
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Table 67 - Serial Character B IT 1
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BIT 3 Framing Error (FE). Bit 3 ind
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D ESIR ED B AU D R AT E D IVISOR US
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7.3.1 EFFECT OF THE RESET ON REGIST
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and the CPU starts to load it. When
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8.1 IRRX/IRTX PIN ENABLE When MISC2
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9 PARALLEL PORT The LPC47N252 incor
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BITS 1, 2 are not implemented as re
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9.1.1.9.2 EPP 1.9 Write The timing
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The chip drives the final sync and
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The bit map of the Extended Paralle
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Table 83 - Extended Control Registe
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9.2.4.7 ister A) - ADDRESS OFFSET =
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9.2.5.2 ECP Operation Prior to ECP
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to 0. The ECP requests DMA transfer
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9.3.3.1 PPPI FDC pin out The FDC si
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Table 90 - FDC_nPP Initiated Pppi M
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Accessing the LPC47N252 during powe
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10.8 UART POWER MANAGEMENT Direct p
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11.2.1 FUNCTIONAL BLOCKS Below are
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System is running (Vcc2 and Vcc1 ar
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KBDCLK[1:0] These 2 bits control th
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FIX BIT REGISTERS SFR REGISTER NAME
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MMCR REGISTER NAME SYSTEM ADDRESS S
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MMCR REGISTER NAME SYSTEM ADDRESS S
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11.8.3.3 Device ID Register By read
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11.8.3.6 8051 LPC Bus Monitor The 8
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IN4 IN5 GPIO0 GPIO1 GPIO2 IN6 GPIO7
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11.9.3 8051 INT0 MASK REGISTER Tabl
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RTC_ALRM asserted [D0] The RTC_ALRM
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Table 118 - Wakeup Source Register
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Table 125 - Wakeup Mask Register 7
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Table 132 - Edge Select 5B HOST ADD
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8051_IRQ ENABLE 8051_IRQ SELECT DES
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12 64K EMBEDDED FLASH ROM 12.1 OVER
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12.3 COMMAND SEQUENCE INTERFACE (CS
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CMD CODE (hex) CSI MODE DESCRIPTION
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12.3.6.1 Busy Bit - D7 The BUSY ind
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12.3.7.2 Read Array Mode READ ARRAY
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12.3.7.4 Page Erase Mode In Page Er
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The CSI host interface and the Flas
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Table 151 - 8051 Flash Boot Block P
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Declarations ERROR_MASK = 0x0070; /
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13 FLASH PROGRAMMING INTERFACE 13.1
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FLASH PROGRAM REGISTER EXT FLASH (D
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FPA[15:8] FPALE FPAD[7:0] nFPRD nFP
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test vector FPA15:8 FPAD7:0 FPALE n
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EFALE nEFRD EFAD[7:0] EFA[15:8] t1
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13.9 DEADMAN SWITCH 13.9.1 OVERVIEW
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13.9.4 DMS REGISTER T P FIGURE 42 -
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13.10.3 EXT FLASH - D3 The EXT FLAS
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13.12 INTERNAL SCRATCH ROM The Kahu
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14.5 WDT MEMORY MAPPED REGISTERS Ta
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15.1.1 EXITING IDLE MODE FIGURE 46
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15.3 WAKE-UP EVENTS N 8051 in sleep
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PIN WAKE-UP EVENTS GPIO11 WK_SE15 W
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16 KEYBOARD CONTROLLER 16.1 8042 ST
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Table 177 - PCOBF HOST N/A 8051 0x7
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SA2 R/W D[0:7] IBF FLAG GATEA20 COM
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FE Command From KRESET Speed up Log
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16.6 DIRECT KEYBOARD SCAN The LPC47
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6) When the controller is ready to
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PS2_T/R PS/2 Channel Transmit/Recei
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If the time from the 1st (start) bi
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When sending a byte to a DEVIL PS/2
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17.6.2 DEVIL PS/2 STATUS REGISTERS
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17.6.5 DEVIL PS/2 RECEIVE REGISTERS
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Table 195 - ACCESS.Bus Register Add
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BIT 7 - PIN Pending Interrupt Not.
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18.2.5 CLOCK REGISTER The Clock Reg
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19 MAILBOX REGISTER INTERFACE 19.1
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19.5 THE SYSTEM/8051 INTERFACE REGI
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System is fully powered & the 8051i
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19.8 FDC SHADOW REGISTERS The LPC47
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20 PULSE WIDTH MODULATORS 20.1 OVER
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MAILBOX INDEX Table 218 - PWM1 Spee
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PWM0 Clock Multiplier, D2 The PWM0
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FAN1 and FAN2 Read Latch registers
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21.5 FAN2 READ LATCH REGISTER The F
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22 8051 CONTROLLED PARALLEL PORT To
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23 HOST CONTROLLED IR PORT It is po
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ITEM TYPE PIN NAMES WAKE CAPABLE BU
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Table 230 - GPIO Input Register A H
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Table 238 -Out Register D HOST ADDR
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24.4.1 LPC LGPIO BASE ADDRESS Logic
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Table 247 - LPC LGPIO Direction Reg
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8051 MMCR ADDRESS REGISTER TYPE 805
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24.4.3.3 8051 LGPIO Group I Registe
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Table 266 - GPIO Buffer Type Config
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24.6 GPIO PASS-THROUGH PORTS The LP
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25 MULTIFUNCTION PIN 25.1 OVERVIEW
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MISC[3,1] - D3 and D1 The MISC3 bit
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Table 286 - Misc14 And Misc13 Bits
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driven open-drain, and the Serial I
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Block base address must be located
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26.5.4 POWER MANAGEMENT 1 ENABLE RE
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27 REAL TIME CLOCK 27.1 GENERAL DES
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The 12/24 bit in Register B establi
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27.7.2 REGISTER B RATE SELECT 32.76
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27.7.6 GENERAL PURPOSE Registers 0x
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27.10 32KHZ CLOCK INPUT The LPC47N2
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Note 1 : “Change” means either-
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1) Quiet (Active) Mode Any device m
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30 XNOR-CHAIN TEST MODE An XNOR-Cha
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31.2.2 CONFIGURATION SEQUENCE EXAMP
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HARD SOFT INDEX TYPE RESET RESET CO
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REGISTER ADDRESS DESCRIPTION PowerC
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LOGICAL DEVICE REGISTER ADDRESS DES
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LOGICAL DEVICE NUMBER LOGICAL DEVIC
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31.9.4 PARALLEL PORT SPP and EPP mo
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NAME REG INDEX DEFINITION FDD0 0xF4
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NAME IR Half Duplex Timeout Default
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PAR AM ETER SYM BOL M IN T YP M AX
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PAR AM ETER IOD 16 Type Bu ff er SY
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32.3 AC SPECIFICATIONS AC Test Cond
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33.2 LPC TIMING CLK Output Delay Tr
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33.3 FLOPPY DISK TIMING nDIR nSTEP
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nWRITE PD nDATASTB nADDRSTB nWAIT t
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33.5 ECP PARALLEL PORT TIMING Paral
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nALF PD nSTROBE BUSY t2 t1 t7 t8 t6
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33.6 SER IA L IRQ TIMIN G PCI_CLK S
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33.9 FAN AND FAN TACHOMETER TIMING
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PS2_CLK PS2_DAT PS2_EN PS2_T/R XMIT
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33.11 FLASH TIMING EFALE nEFRD EFAD
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FIGURE 102 - 208 PIN FL EX BGA 15.0
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INSTRUCTION DESCRIPTION BYTE COUNT
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INSTRUCTION DESCRIPTION BYTE COUNT
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The LPC47N252 adds a second data po
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Table 333 - CKCON Register - SFR 8E
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TL2 The TL2 register (Table 340) is
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Table 345 - Eicon Register Bit Desc
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SMSC LPC47N252 Data Sheet - Keil

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