SMSC LPC47N252 Data Sheet - Keil

BIT 7 DSKCHG
This bit monitors the pin of the same name and reflects the opposite value seen on the disk cable or the value
programmed in the Disk Change Register (see section 19.8, FDC Shadow Registers System on page 229.)
CONFIGURATION CONTROL REGISTER (CCR)
FDC I/O Base Address + 0x07 (WRITE ONLY)
R ESET
C ON D.
Table 39 - FDC CCR PC/AT an d PS/2 M od e
7 6 5 4 3 2 1 0
D RATE
SEL1
D RATE
SEL0
N /A N /A N /A N /A N /A N /A 1 0
BIT 0 and 1 DATA RATE SELECT 0 and 1
These bits determine the data rate of the floppy controller. See Table 31 for the appropriate values.
BIT 2 - 7 RESERVED
Should be set to a logical "0"
R ESET
C ON D.
Table 40 - FDC CCR - PS/2 M od el 30 M o de
7 6 5 4 3 2 1 0
N OPREC D RATE
SEL1
D RATE
SEL0
N /A N /A N /A N /A N /A N /A 1 0
BIT 0 and 1 DATA RATE SELECT 0 and 1
These bits determine the data rate of the floppy controller. See Table 31 for the appropriate values.
BIT 2 NO PRECOMPENSATION
This bit can be set by software, but it has no functionality. It can be read by bit 2 of the DSR when in Model 30
register mode. Unaffected by software reset.
BIT 3 - 7 RESERVED
Should be set to a logical "0"
Table 31 shows the state of the DENSEL pin. The DENSEL pin is set high after a hardware reset and is unaffected
by the DOR and the DSR resets.
STATUS REGISTER ENCODING
During the Result Phase of certain commands, the Data Register contains data bytes that give the status of the
command just executed.
SMSC DS – LPC47N252 Page 48 Rev. 09/06/2000