SMSC LPC47N252 Data Sheet - Keil

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TQFP PIN NOTES NAME DESCRIPTION 189 Note 5 GPIO5 (WK_SE10)/ KSO15 190 Note 5 GPIO6 (WK_SE11)/ IRMODE/IRRX 3A 191 Note 5, Note 8 GPIO7 (WK_SE06) 141 Note 5 GPIO8 (WK_SE12)/ IRRX2 142 Note 1, Note 5 GPIO9 (WK_SE13)/ IRTX2 145 Note 5 GPIO10 (WK_SE14)/ IRMODE/IRRX 3B 146 Note 5 GPIO11 (WK_SE15)/ AB2A_DATA 147 Note 5 GPIO12 (WK_SE16) AB2A_CLK 144 Note 5 GPIO13 (WK_SE17) AB2B_DATA 140 Note 5 GPIO14 (WK_SE20) AB2B_CLK 139 Note 5 GPIO15 (WK_SE21) FAN_TACH1 204 Note 5 GPIO16 (WK_SE22) FAN_TACH2 206 Note 3, Note 5 GPIO17 (WK_SE23)/ A20M 208 Note 5 GPIO19 (WK_SE24) 45 Note 3, Note 5 46 Note 3, Note 5 GPIO20 (WK_SE25) 5 / PS2CLK/ 8051RX/ GPIO21 (WK_SE26) 5 / PS2DAT/ 8051TX 54:61 SGPIO30 – SGPIO37 207, 63:69 SGPIO40 – SGPIO47 76:84 LGPIO50 – LGPIO57 85:90 163:165 LGPIO60 – LGPIO67 General Purpose I/O Keyboard Scan Output General Purpose I/O FIR Mode Output or 2 nd Receive Input POWER PLANE BUFFER MODES 2 VCC1 IO8/OD8 VCC1 IO8/(O8/I) General Purpose I/O VCC1 (IO8/IOD8) 8 General Purpose I/O IR Receive Input General Purpose I/O IR Transmit Output General Purpose I/O FIR Mode Output or 2 nd Receive Input General Purpose I/O ACCESS.Bus 2 Serial Data (switch position A) General Purpose I/O ACCESS.Bus 2 Clock (switch position A) General Purpose I/O ACCESS.Bus 2 Serial Data (switch position B) General Purpose I/O ACCESS.Bus 2 Clock (switch position B) General Purpose I/O Fan Tachometer Input 1 General Purpose I/O Fan Tachometer Input 2 General Purpose I/O KBD GATEA20 Output 3 VCC1 IO8/I VCC1 IO12/O12 VCC1 IO8/O8/(O8/I) VCC1 IO12 /IOD12 VCC1 IO12 /IOD12 VCC1 IO12 /IOD12 VCC1 IO12 /IOD12 VCC1 IO8/I VCC1 IO8/I VCC1 IO8/O8 General Purpose I/O VCC1 IO8 General Purpose I/O PS2 Serial Clock 3 8051 RX Input General Purpose I/O PS2 Serial Data 3 8051 TX Input VCC1 IOD16/IOD16/I VCC1 IOD16/IOD16/O D16 8051 SFR bit-wise addressable GPIO VCC1 IO8/(O8/I) 8051 SFR bit-wise addressable GPIO VCC1 IO8/(O8/I) LPC General Purpose I/O VCC1 IO8 LPC General Purpose I/O VCC1 IO8 SMSC DS – LPC47N252 Page 18 Rev. 09/06/2000
TQFP PIN NOTES NAME DESCRIPTION 166, 168:174 LGPIO70 – LGPIO77 POWER PLANE BUFFER MODES 2 LPC General Purpose I/O VCC1 IO8 INFRARED INTERFACE (2) 21 IRRX IR Receive Input VCC1 I 20 Note 1 IRTX IR Transmit Output VCC2 O12 126 nINIT/ nDIR 125 nSLCTIN/ nSTEP 124 PD0/ nINDEX 123 PD1/ nTRK0 122 PD2/ nWRTPRT 121 PD3/ nRDATA 119 PD4/ nDSKCHG PARALLEL PORT INTERFACE (17) I nitia te O u tp ut F DC Dire ct ion Co nt ro l Print e r Se lect Inp ut F DC St ep Pu lse Por t Dat a 0 F DC I n de x Por t Dat a 1 F DC T r ack 0 Por t Dat a 2 F DC Wr it e Pro te cte d Por t Dat a 3 F DC Re ad Disk Da ta Por t Dat a 4 F DC Disk Ch an ge VCC2 ( OD14 / OP14 ) / O D1 4 VCC2 ( OD14 / OP14 ) / O D1 4 VCC2 I OP14 / I VCC2 I OP14 / I VCC2 I OP14 / I VCC2 I OP14 / I VCC2 I OP14 / I 118 PD5 Por t Dat a 5 VCC2 I OP14 117 PD6/ nMTR0 Por t Dat a 6 F DC M o to r On 0 VCC2 I OP14 / OD14 116 PD7 Por t Dat a 7 VCC2 I OP14 112 SLCT/ nWGATE 113 PE/ nWDATA 114 BUSY/ nMTR1 115 nACK/ nDS1 127 nERROR/ nHDSEL 128 nALF/ DRVDEN0 129 nSTROBE/ nDS0 Print e r Se lecte d Sta t us F DC Wr it e Gat e Pap er En d F DC Wr it e Dat a Busy F DC M o to r On 1 Ackno wle dg e F DC Dr ive Select 1 Err or F DC He ad Se le ct Aut of e ed O u tp ut F DC De nsit y Sele ct 0 Str ob e O ut p ut F DC Dr ive Select 0 SERIAL PORT INTERFACE (8) VCC2 I /O D1 2 VCC2 I /O D1 2 VCC2 I /O D1 2 VCC2 I /O D1 2 VCC2 I /O D1 2 VCC2 ( OD14 / OP14 ) /O D14 VCC2 ( OD14 / OP14 ) /O D14 130 RXD Receive Data VCC2 I 131 TXD Transmit Data VCC2 O12 133 nDSR Data Set Ready VCC2 I 134 nRTS Request to Send VCC2 O8 135 nCTS Clear to Send VCC2 I 136 nDTR Data Terminal Ready VCC2 O8 138 nRI Ring Indicator VCC1 I 137 nDCD Data Carrier Detect VCC2 I MISCELLANEOUS (17) 108 32kHz_OUT 32.768kHz Output Clock VCC1 O8 105 24MHz_OUT 24MHz Clock Output VCC2 O24 103 CLOCKI 14.318MHz Clock Input VCC2 ICLK 1 Note 18 MODE Configuration Ports Base Address Select VCC1 I 157 Note 10 XOSEL 10 External 32kHz Clock Enable Input VCC0 I 109 Note 9 VCC1_PWRGD VCC1 Power Good Input VCC1 I SMSC DS – LPC47N252 Page 19 Rev. 09/06/2000
Page 1 and 2: _ Advanced Notebook I/O Controller
Page 3 and 4: GENERAL DESCRIPTION The LPC47N252 i
Page 5 and 6: 5.7.1 Read Data....................
Page 7 and 8: 12.2 FLASH MEMORY ARRAY ...........
Page 9 and 10: 21.1 FAN TACHOMETER OVERVIEW ......
Page 11 and 12: APPENDIX A: HIGH-PERFORMANCE 8051 C
Page 13 and 14: SMSC DS - LPC47N252 Page 13 Rev. 09
Page 15 and 16: 3 PIN FUNCTIONS TQFP PIN # FBGA NAM
Page 17: TQFP PIN NOTES NAME DESCRIPTION 44:
Page 21 and 22: Note 8: OUT0 and GPIO7 are suitable
Page 23 and 24: DEFAULT FUNCTION PWR ALTERNATE FUNC
Page 25 and 26: 4 FUNCTIONAL DESCRIPTION The host p
Page 27 and 28: Table 6 - Basic Lpc Bus Cycle Descr
Page 29 and 30: 4.1.7.1 DMA Acknowledge The DMA ack
Page 31 and 32: 4.1.8.4 Sync Error Indication The p
Page 33 and 34: FIELD DRIVEN BY CLOCKS LAD[3:0] COM
Page 35 and 36: FIELD DRIVEN BY CLOCKS LAD[3:0] COM
Page 37 and 38: state (ACPI S1, APM POS), LPCPD# ma
Page 39 and 40: BIT 4 nTRACK 0 Active low status of
Page 41 and 42: BIT 3 READ DATA Active high status
Page 43 and 44: Enhanced Floppy Mode 2 (OS2) TAPE S
Page 45 and 46: 10 = 2 Meg Tape Note 1: The DRATE a
Page 47 and 48: BIT 0 - 6 UNDEFINED The data bus ou
Page 49 and 50: Table 41 - FDC Status Register 0 B
Page 51 and 52: DOR Reset vs. DSR Reset (Software R
Page 53 and 54: RQM and DIO must both equal "1" bef
Page 55 and 56: 5.6 FDC INSTRUCTION SET Table 46 -
Page 57 and 58: R EA D A T RA C K D AT A B US PHA S
Page 59 and 60: SPECIF Y D AT A B US PHA SE R /W D
Page 61 and 62: INVAL ID COD ES D AT A B US PHA SE
Page 63 and 64: SK BIT VAL UE 5.7.3 READ A TRACK Ta
Page 65 and 66: Table 52 - Verify Command Result Ph
Page 67 and 68: 5.8 FDC CONTROL COMMANDS Control co
Page 69 and 70:
0 1 .. E F 00 01 02 .. 7F 7F Table
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Gap2 field is expanded to a length
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MECHANISM FDC OUTPUT PINS STATE FDC
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6 ACPI EMBEDDED CONTROLLER ACPI def
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Once the host reads the data, the O
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7 SERIAL PORT (UART) The LPC47N252
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7.1.5 INTERRUPT IDENTIFICATION REGI
Page 83 and 84:
Table 67 - Serial Character B IT 1
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BIT 3 Framing Error (FE). Bit 3 ind
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D ESIR ED B AU D R AT E D IVISOR US
Page 89 and 90:
7.3.1 EFFECT OF THE RESET ON REGIST
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and the CPU starts to load it. When
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8.1 IRRX/IRTX PIN ENABLE When MISC2
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9 PARALLEL PORT The LPC47N252 incor
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BITS 1, 2 are not implemented as re
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9.1.1.9.2 EPP 1.9 Write The timing
Page 101 and 102:
The chip drives the final sync and
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The bit map of the Extended Paralle
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Table 83 - Extended Control Registe
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9.2.4.7 ister A) - ADDRESS OFFSET =
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9.2.5.2 ECP Operation Prior to ECP
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to 0. The ECP requests DMA transfer
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9.3.3.1 PPPI FDC pin out The FDC si
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Table 90 - FDC_nPP Initiated Pppi M
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Accessing the LPC47N252 during powe
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10.8 UART POWER MANAGEMENT Direct p
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11.2.1 FUNCTIONAL BLOCKS Below are
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System is running (Vcc2 and Vcc1 ar
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KBDCLK[1:0] These 2 bits control th
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FIX BIT REGISTERS SFR REGISTER NAME
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MMCR REGISTER NAME SYSTEM ADDRESS S
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MMCR REGISTER NAME SYSTEM ADDRESS S
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11.8.3.3 Device ID Register By read
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11.8.3.6 8051 LPC Bus Monitor The 8
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IN4 IN5 GPIO0 GPIO1 GPIO2 IN6 GPIO7
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11.9.3 8051 INT0 MASK REGISTER Tabl
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RTC_ALRM asserted [D0] The RTC_ALRM
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Table 118 - Wakeup Source Register
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Table 125 - Wakeup Mask Register 7
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Table 132 - Edge Select 5B HOST ADD
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8051_IRQ ENABLE 8051_IRQ SELECT DES
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12 64K EMBEDDED FLASH ROM 12.1 OVER
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12.3 COMMAND SEQUENCE INTERFACE (CS
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CMD CODE (hex) CSI MODE DESCRIPTION
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12.3.6.1 Busy Bit - D7 The BUSY ind
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12.3.7.2 Read Array Mode READ ARRAY
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12.3.7.4 Page Erase Mode In Page Er
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The CSI host interface and the Flas
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Table 151 - 8051 Flash Boot Block P
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Declarations ERROR_MASK = 0x0070; /
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13 FLASH PROGRAMMING INTERFACE 13.1
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FLASH PROGRAM REGISTER EXT FLASH (D
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FPA[15:8] FPALE FPAD[7:0] nFPRD nFP
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test vector FPA15:8 FPAD7:0 FPALE n
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EFALE nEFRD EFAD[7:0] EFA[15:8] t1
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13.9 DEADMAN SWITCH 13.9.1 OVERVIEW
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13.9.4 DMS REGISTER T P FIGURE 42 -
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13.10.3 EXT FLASH - D3 The EXT FLAS
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13.12 INTERNAL SCRATCH ROM The Kahu
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14.5 WDT MEMORY MAPPED REGISTERS Ta
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15.1.1 EXITING IDLE MODE FIGURE 46
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15.3 WAKE-UP EVENTS N 8051 in sleep
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PIN WAKE-UP EVENTS GPIO11 WK_SE15 W
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16 KEYBOARD CONTROLLER 16.1 8042 ST
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Table 177 - PCOBF HOST N/A 8051 0x7
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SA2 R/W D[0:7] IBF FLAG GATEA20 COM
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FE Command From KRESET Speed up Log
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16.6 DIRECT KEYBOARD SCAN The LPC47
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6) When the controller is ready to
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PS2_T/R PS/2 Channel Transmit/Recei
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If the time from the 1st (start) bi
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When sending a byte to a DEVIL PS/2
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17.6.2 DEVIL PS/2 STATUS REGISTERS
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17.6.5 DEVIL PS/2 RECEIVE REGISTERS
Page 217 and 218:
Table 195 - ACCESS.Bus Register Add
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BIT 7 - PIN Pending Interrupt Not.
Page 221 and 222:
18.2.5 CLOCK REGISTER The Clock Reg
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19 MAILBOX REGISTER INTERFACE 19.1
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19.5 THE SYSTEM/8051 INTERFACE REGI
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System is fully powered & the 8051i
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19.8 FDC SHADOW REGISTERS The LPC47
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20 PULSE WIDTH MODULATORS 20.1 OVER
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MAILBOX INDEX Table 218 - PWM1 Spee
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PWM0 Clock Multiplier, D2 The PWM0
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FAN1 and FAN2 Read Latch registers
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21.5 FAN2 READ LATCH REGISTER The F
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22 8051 CONTROLLED PARALLEL PORT To
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23 HOST CONTROLLED IR PORT It is po
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ITEM TYPE PIN NAMES WAKE CAPABLE BU
Page 247 and 248:
Table 230 - GPIO Input Register A H
Page 249 and 250:
Table 238 -Out Register D HOST ADDR
Page 251 and 252:
24.4.1 LPC LGPIO BASE ADDRESS Logic
Page 253 and 254:
Table 247 - LPC LGPIO Direction Reg
Page 255 and 256:
8051 MMCR ADDRESS REGISTER TYPE 805
Page 257 and 258:
24.4.3.3 8051 LGPIO Group I Registe
Page 259 and 260:
Table 266 - GPIO Buffer Type Config
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24.6 GPIO PASS-THROUGH PORTS The LP
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25 MULTIFUNCTION PIN 25.1 OVERVIEW
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MISC[3,1] - D3 and D1 The MISC3 bit
Page 267 and 268:
Table 286 - Misc14 And Misc13 Bits
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driven open-drain, and the Serial I
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Block base address must be located
Page 273 and 274:
26.5.4 POWER MANAGEMENT 1 ENABLE RE
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27 REAL TIME CLOCK 27.1 GENERAL DES
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The 12/24 bit in Register B establi
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27.7.2 REGISTER B RATE SELECT 32.76
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27.7.6 GENERAL PURPOSE Registers 0x
Page 283 and 284:
27.10 32KHZ CLOCK INPUT The LPC47N2
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Note 1 : “Change” means either-
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1) Quiet (Active) Mode Any device m
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30 XNOR-CHAIN TEST MODE An XNOR-Cha
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31.2.2 CONFIGURATION SEQUENCE EXAMP
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HARD SOFT INDEX TYPE RESET RESET CO
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REGISTER ADDRESS DESCRIPTION PowerC
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LOGICAL DEVICE REGISTER ADDRESS DES
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LOGICAL DEVICE NUMBER LOGICAL DEVIC
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31.9.4 PARALLEL PORT SPP and EPP mo
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NAME REG INDEX DEFINITION FDD0 0xF4
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NAME IR Half Duplex Timeout Default
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PAR AM ETER SYM BOL M IN T YP M AX
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PAR AM ETER IOD 16 Type Bu ff er SY
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32.3 AC SPECIFICATIONS AC Test Cond
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33.2 LPC TIMING CLK Output Delay Tr
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33.3 FLOPPY DISK TIMING nDIR nSTEP
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nWRITE PD nDATASTB nADDRSTB nWAIT t
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33.5 ECP PARALLEL PORT TIMING Paral
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nALF PD nSTROBE BUSY t2 t1 t7 t8 t6
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33.6 SER IA L IRQ TIMIN G PCI_CLK S
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33.9 FAN AND FAN TACHOMETER TIMING
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PS2_CLK PS2_DAT PS2_EN PS2_T/R XMIT
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33.11 FLASH TIMING EFALE nEFRD EFAD
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FIGURE 102 - 208 PIN FL EX BGA 15.0
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INSTRUCTION DESCRIPTION BYTE COUNT
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INSTRUCTION DESCRIPTION BYTE COUNT
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The LPC47N252 adds a second data po
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Table 333 - CKCON Register - SFR 8E
Page 341 and 342:
TL2 The TL2 register (Table 340) is
Page 343 and 344:
Table 345 - Eicon Register Bit Desc
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SMSC LPC47N252 Data Sheet - Keil

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