SMSC LPC47N252 Data Sheet - Keil

TABLE OF CONTENTS
FEATURES .................................................................................................................................................................. 1
GENERAL DESCRIPTION........................................................................................................................................ 3
1.1 REFERENCE DOCUMENTS................................................................................................................................. 12
1.1.1 Intel Low Pin Count Specification ......................................................................................................... 12
1.1.2 PCI Local Bus Specification.................................................................................................................. 12
1.1.3 Advanced Configuration and Power Interface Specification................................................................. 12
1.1.4 LPC47N252 Notebook I/O Controller with Enhanced Keyboard Control and System Management.... 12
1.1.5 IEEE 1284 Extended Capabilities Port Protocol and ISA Interface Standard ...................................... 12
2 TQFP PIN CONFIGURATION.............................................................................................................................. 13
3 PIN FUNCTIONS.................................................................................................................................................. 15
3.1 DESCRIPTION OF PIN FUNCTIONS ..................................................................................................................... 16
3.1.1 Alternate Function Pins........................................................................................................................ 22
3.2 POWER CONFIGURATION.................................................................................................................................. 23
4 FUNCTIONAL DESCRIPTION............................................................................................................................. 25
4.1 HOST PROCESSOR INTERFACE (LPC) ............................................................................................................... 26
4.1.1 LPC Bus Cycles Description................................................................................................................ 26
4.1.2 LPC Bus Cycles Summary ................................................................................................................... 27
4.1.3 Standard LFRAME# Usage .................................................................................................................. 27
4.1.4 Abort Mechanism.................................................................................................................................. 28
4.1.5 I/O Read And Write Cycles................................................................................................................... 28
4.1.6 Dma Read And Write Cycles................................................................................................................ 28
4.1.7 DMA Request ....................................................................................................................................... 28
4.1.8 SYNC Protocol...................................................................................................................................... 30
4.1.9 I/O And DMA Start Fields ..................................................................................................................... 31
4.1.10 Reset Policy.......................................................................................................................................... 31
4.1.11 Electrical Specifications........................................................................................................................ 31
4.1.12 Wait State Requirements...................................................................................................................... 31
4.1.13 LPC Transfer Sequence Examples ...................................................................................................... 31
4.1.14 LPC Power Management...................................................................................................................... 36
5 FLOPPY DISK CONTROLLER............................................................................................................................ 38
FDC INTERNAL REGISTERS.......................................................................................................................................... 38
Status Register A (SRA)....................................................................................................................................... 38
Status Register B (SRB)....................................................................................................................................... 39
Digital Output Register (DOR) .............................................................................................................................. 41
Tape Drive Register (TDR)................................................................................................................................... 42
Data Rate Select Register (DSR) ......................................................................................................................... 43
Main Status Register ............................................................................................................................................ 45
Data Register (FIFO) ............................................................................................................................................ 46
Digital Input Register (DIR)................................................................................................................................... 46
Configuration Control Register (CCR) .................................................................................................................. 48
STATUS REGISTER ENCODING............................................................................................................................ 48
5.1 FDC RESET ................................................................................................................................................. 50
5.2 FDC MODES OF OPERATION.................................................................................................................... 51
5.2.1 PC/AT mode ......................................................................................................................................... 51
5.2.2 PS/2 mode............................................................................................................................................ 51
5.2.3 Model 30 mode..................................................................................................................................... 51
5.3 DMA TRANSFERS....................................................................................................................................... 51
5.4 CONTROLLER PHASES.............................................................................................................................. 51
5.4.1 Command Phase.................................................................................................................................. 51
5.4.2 Execution Phase................................................................................................................................... 51
5.4.3 Result Phase ........................................................................................................................................ 52
5.5 COMMAND SET/DESCRIPTIONS............................................................................................................... 53
5.6 FDC INSTRUCTION SET............................................................................................................................. 55
5.7 FDC DATA TRANSFER COMMANDS......................................................................................................... 61
SMSC DS – LPC47N252 Page 4 Rev. 09/06/2000