SMSC LPC47N252 Data Sheet - Keil

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− VCC1 and VCC2 operation mode � Dual Fan Tachometer Inputs � 2.88MB Super I/O Floppy Disk Controller − Relocatable to 480 Different Base I/O Addresses − 15 IRQ Options − 4 DMA Options − Open-Drain/Push-Pull Configurable Output Drivers − Licensed CMOS 765B Floppy Disk Controller − Advanced Digital Data Separator − Software and Register Compatible with SMSC's Proprietary 82077AA Compatible Core − Low Power CMOS Design with Sophisticated Power Control Circuitry (PCC) Including Multiple Powerdown Modes for Reduced Power Consumption − Supports Two Floppy Drives on the FDD Interface and Two Floppy Drives on the Parallel Port Interface − 12 mA FDD Interface Cable Drivers with Schmitt Trigger Inputs � Licensed CMOS 765B Floppy Disk Controller Core − Supports Vertical Recording Format − 16-Byte Data FIFO − 100% IBM Compatibility − Detects All Overrun and Underrun Conditions − 12 mA Drivers and Schmitt Trigger Inputs − DMA Enable Logic − Data Rate and Drive Control Registers ORDERING INFORMATION Order Numbers: LPC47N252-SG for 208 Pin FBGA Package LPC47N252-SD for 208 Pin TQFP Package � Enhanced Digital Data Separator − Low Cost Implementation − No Filter Components Required − 2 Mbps, 1 Mbps, 500 Kbps, 300 Kbps, 250 Kbps Data Rates − Programmable Precompensation Modes � Multi-Mode Parallel Port with ChiProtect − Standard Mode IBM PC/XT, PC/AT, and PS/2 Compatible Bi-directional Parallel Port − Enhanced Parallel Port EPP 1.7 and EPP 1.9 Compatible (IEEE 1284 Compliant) − IEEE 1284 Compliant Enhanced Capabilities Port (ECP) − ChiProtect Circuitry to Prevent Printer Power-On Damage − Relocatable to 480 Different Base I/O Addresses − 15 IRQ Options − 4 DMA Options − Microsoft and HP compatible High Speed Mode − Floppy Disk Interface on Parallel Port − 8051-Controlled Parallel Port Mode � Serial Port − High-Speed NS16550A-Compatible UART with 16-Byte Send/Receive FIFOs − Programmable Baud Rate Generator − Modem Control Circuitry Including 230k and 460k Baud − Relocatable to 480 Different Base I/O Addresses − 15 IRQ Options SMSC DS - LPC47N252 Page 2 Rev. 09/06/2000
GENERAL DESCRIPTION The LPC47N252 is a 208-pin 3.3V LPC-based ACPI 1.0 and PC99/PC2001 compliant Notebook I/O Controller with Fast Infrared for mobile applications. See FIGURE 2 – LPC47N252 BLOCK DIAGRAM. The LPC47N252 incorporates a high-performance 8051-based keyboard controller; a 64k byte internal Flash ROM, four PS/2 ports; a real-time clock; SMSC's true CMOS 765B floppy disk controller with advanced digital data separator and 16-byte data FIFO; an NS16C550A-compatible UART, SMSC’s advanced Infrared Communications Controller (IrCC 2.0) with a UART and a Synchronous Communications Engine to provide IrDA v1.1 (Fast IR) capabilities; one Multi-Mode parallel port with ChiProtect circuitry plus EPP and ECP support; two 8584-style Access Bus controllers with two Sets of Dedicated Pins per ACCESS.Bus Controller; a Serial IRQ peripheral agent interface; an ACPI Embedded Controller Interface; General Purpose I/O pins including eight pass through ports; three independently programmable pulse width modulators; two-floppy direct drive support; and maskable hardware wakeup events. The true CMOS 765B core provides 100% compatibility with IBM PC/XT and PC/AT architectures in addition to providing data overflow and underflow protection. The SMSC advanced digital data separator incorporates SMSC's patented data separator technology, allowing for ease of testing and use. The parallel port is compatible with IBM PC/AT architecture, as well as EPP and ECP. The 8051 controller can also take control of the parallel port interface to provide remote diagnostics or “Flashing” of the Flash memory. The LPC47N252 has three separate power planes to provide “instant on” and system power management functions. Additionally, the LPC47N252 incorporates sophisticated power control circuitry (PCC). The PCC supports multiple low power down modes. Wake-up events and ACPI-related functions are supported through the SCI Interface. The LPC47N252’s configuration register set is compatible with the ISA Plug-and-Play Standard (Version 1.0a) and provides the functionality to support Windows '95.The legacy host Super I/O Configuration and Alternate Super I/O Configuration decode ranges comply with the Low Pin Count Interface Specification, Revision 1.0. Through internal configuration registers, each of the LPC47N252's logical device's I/O address, DMA channel and IRQ channel may be programmed. There are 480 I/O address location options, 15 IRQ options, and four DMA channel options for each logical device. The LPC47N252 does not require any external filter components and is, therefore, easy to use and offers lower system cost and reduced board area. The LPC47N252 is software and register compatible with SMSC's proprietary 82077AA core. © STANDARD MICROSYSTEMS CORPORATION (SMSC) 2000 80 Arkay Drive Hauppauge, NY 11788 (631) 435-6000 FAX (631) 273-3123 Standard Microsystems is a registered trademark of Standard Microsystems Corporation, and SMSC, Ultra I/O, ChiProtect, and Multi-Mode are trademarks of Standard Microsystems Corporation. Product names and company names are the trademarks of their respective holders. Circuit diagrams utilizing SMSC products are included as a means of illustrating typical applications; consequently complete information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does not convey to the purchaser of the semiconductor devices described any licenses under the patent rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com. SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT, AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES, OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT, TORT, NEGLIGENCE OF SMSC OR OTHERS, STRICT LIABILITY, BREACH OF WARRANTY, OR OTHERWISE; WHETHER OR NOT ANY REMEDY IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE; AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. SMSC DS – LPC47N252 Page 3 Rev. 09/06/2000
Page 1: _ Advanced Notebook I/O Controller
Page 5 and 6: 5.7.1 Read Data....................
Page 7 and 8: 12.2 FLASH MEMORY ARRAY ...........
Page 9 and 10: 21.1 FAN TACHOMETER OVERVIEW ......
Page 11 and 12: APPENDIX A: HIGH-PERFORMANCE 8051 C
Page 13 and 14: SMSC DS - LPC47N252 Page 13 Rev. 09
Page 15 and 16: 3 PIN FUNCTIONS TQFP PIN # FBGA NAM
Page 17 and 18: TQFP PIN NOTES NAME DESCRIPTION 44:
Page 19 and 20: TQFP PIN NOTES NAME DESCRIPTION 166
Page 21 and 22: Note 8: OUT0 and GPIO7 are suitable
Page 23 and 24: DEFAULT FUNCTION PWR ALTERNATE FUNC
Page 25 and 26: 4 FUNCTIONAL DESCRIPTION The host p
Page 27 and 28: Table 6 - Basic Lpc Bus Cycle Descr
Page 29 and 30: 4.1.7.1 DMA Acknowledge The DMA ack
Page 31 and 32: 4.1.8.4 Sync Error Indication The p
Page 33 and 34: FIELD DRIVEN BY CLOCKS LAD[3:0] COM
Page 35 and 36: FIELD DRIVEN BY CLOCKS LAD[3:0] COM
Page 37 and 38: state (ACPI S1, APM POS), LPCPD# ma
Page 39 and 40: BIT 4 nTRACK 0 Active low status of
Page 41 and 42: BIT 3 READ DATA Active high status
Page 43 and 44: Enhanced Floppy Mode 2 (OS2) TAPE S
Page 45 and 46: 10 = 2 Meg Tape Note 1: The DRATE a
Page 47 and 48: BIT 0 - 6 UNDEFINED The data bus ou
Page 49 and 50: Table 41 - FDC Status Register 0 B
Page 51 and 52: DOR Reset vs. DSR Reset (Software R
Page 53 and 54:
RQM and DIO must both equal "1" bef
Page 55 and 56:
5.6 FDC INSTRUCTION SET Table 46 -
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R EA D A T RA C K D AT A B US PHA S
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SPECIF Y D AT A B US PHA SE R /W D
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INVAL ID COD ES D AT A B US PHA SE
Page 63 and 64:
SK BIT VAL UE 5.7.3 READ A TRACK Ta
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Table 52 - Verify Command Result Ph
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5.8 FDC CONTROL COMMANDS Control co
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0 1 .. E F 00 01 02 .. 7F 7F Table
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Gap2 field is expanded to a length
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MECHANISM FDC OUTPUT PINS STATE FDC
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6 ACPI EMBEDDED CONTROLLER ACPI def
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Once the host reads the data, the O
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7 SERIAL PORT (UART) The LPC47N252
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7.1.5 INTERRUPT IDENTIFICATION REGI
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Table 67 - Serial Character B IT 1
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BIT 3 Framing Error (FE). Bit 3 ind
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D ESIR ED B AU D R AT E D IVISOR US
Page 89 and 90:
7.3.1 EFFECT OF THE RESET ON REGIST
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and the CPU starts to load it. When
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8.1 IRRX/IRTX PIN ENABLE When MISC2
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9 PARALLEL PORT The LPC47N252 incor
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BITS 1, 2 are not implemented as re
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9.1.1.9.2 EPP 1.9 Write The timing
Page 101 and 102:
The chip drives the final sync and
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The bit map of the Extended Paralle
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Table 83 - Extended Control Registe
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9.2.4.7 ister A) - ADDRESS OFFSET =
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9.2.5.2 ECP Operation Prior to ECP
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to 0. The ECP requests DMA transfer
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9.3.3.1 PPPI FDC pin out The FDC si
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Table 90 - FDC_nPP Initiated Pppi M
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Accessing the LPC47N252 during powe
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10.8 UART POWER MANAGEMENT Direct p
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11.2.1 FUNCTIONAL BLOCKS Below are
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System is running (Vcc2 and Vcc1 ar
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KBDCLK[1:0] These 2 bits control th
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FIX BIT REGISTERS SFR REGISTER NAME
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MMCR REGISTER NAME SYSTEM ADDRESS S
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MMCR REGISTER NAME SYSTEM ADDRESS S
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11.8.3.3 Device ID Register By read
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11.8.3.6 8051 LPC Bus Monitor The 8
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IN4 IN5 GPIO0 GPIO1 GPIO2 IN6 GPIO7
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11.9.3 8051 INT0 MASK REGISTER Tabl
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RTC_ALRM asserted [D0] The RTC_ALRM
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Table 118 - Wakeup Source Register
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Table 125 - Wakeup Mask Register 7
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Table 132 - Edge Select 5B HOST ADD
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8051_IRQ ENABLE 8051_IRQ SELECT DES
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12 64K EMBEDDED FLASH ROM 12.1 OVER
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12.3 COMMAND SEQUENCE INTERFACE (CS
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CMD CODE (hex) CSI MODE DESCRIPTION
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12.3.6.1 Busy Bit - D7 The BUSY ind
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12.3.7.2 Read Array Mode READ ARRAY
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12.3.7.4 Page Erase Mode In Page Er
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The CSI host interface and the Flas
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Table 151 - 8051 Flash Boot Block P
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Declarations ERROR_MASK = 0x0070; /
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13 FLASH PROGRAMMING INTERFACE 13.1
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FLASH PROGRAM REGISTER EXT FLASH (D
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FPA[15:8] FPALE FPAD[7:0] nFPRD nFP
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test vector FPA15:8 FPAD7:0 FPALE n
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EFALE nEFRD EFAD[7:0] EFA[15:8] t1
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13.9 DEADMAN SWITCH 13.9.1 OVERVIEW
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13.9.4 DMS REGISTER T P FIGURE 42 -
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13.10.3 EXT FLASH - D3 The EXT FLAS
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13.12 INTERNAL SCRATCH ROM The Kahu
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14.5 WDT MEMORY MAPPED REGISTERS Ta
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15.1.1 EXITING IDLE MODE FIGURE 46
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15.3 WAKE-UP EVENTS N 8051 in sleep
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PIN WAKE-UP EVENTS GPIO11 WK_SE15 W
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16 KEYBOARD CONTROLLER 16.1 8042 ST
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Table 177 - PCOBF HOST N/A 8051 0x7
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SA2 R/W D[0:7] IBF FLAG GATEA20 COM
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FE Command From KRESET Speed up Log
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16.6 DIRECT KEYBOARD SCAN The LPC47
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6) When the controller is ready to
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PS2_T/R PS/2 Channel Transmit/Recei
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If the time from the 1st (start) bi
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When sending a byte to a DEVIL PS/2
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17.6.2 DEVIL PS/2 STATUS REGISTERS
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17.6.5 DEVIL PS/2 RECEIVE REGISTERS
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Table 195 - ACCESS.Bus Register Add
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BIT 7 - PIN Pending Interrupt Not.
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18.2.5 CLOCK REGISTER The Clock Reg
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19 MAILBOX REGISTER INTERFACE 19.1
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19.5 THE SYSTEM/8051 INTERFACE REGI
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System is fully powered & the 8051i
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19.8 FDC SHADOW REGISTERS The LPC47
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20 PULSE WIDTH MODULATORS 20.1 OVER
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MAILBOX INDEX Table 218 - PWM1 Spee
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PWM0 Clock Multiplier, D2 The PWM0
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FAN1 and FAN2 Read Latch registers
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21.5 FAN2 READ LATCH REGISTER The F
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22 8051 CONTROLLED PARALLEL PORT To
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23 HOST CONTROLLED IR PORT It is po
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ITEM TYPE PIN NAMES WAKE CAPABLE BU
Page 247 and 248:
Table 230 - GPIO Input Register A H
Page 249 and 250:
Table 238 -Out Register D HOST ADDR
Page 251 and 252:
24.4.1 LPC LGPIO BASE ADDRESS Logic
Page 253 and 254:
Table 247 - LPC LGPIO Direction Reg
Page 255 and 256:
8051 MMCR ADDRESS REGISTER TYPE 805
Page 257 and 258:
24.4.3.3 8051 LGPIO Group I Registe
Page 259 and 260:
Table 266 - GPIO Buffer Type Config
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24.6 GPIO PASS-THROUGH PORTS The LP
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25 MULTIFUNCTION PIN 25.1 OVERVIEW
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MISC[3,1] - D3 and D1 The MISC3 bit
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Table 286 - Misc14 And Misc13 Bits
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driven open-drain, and the Serial I
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Block base address must be located
Page 273 and 274:
26.5.4 POWER MANAGEMENT 1 ENABLE RE
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27 REAL TIME CLOCK 27.1 GENERAL DES
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The 12/24 bit in Register B establi
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27.7.2 REGISTER B RATE SELECT 32.76
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27.7.6 GENERAL PURPOSE Registers 0x
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27.10 32KHZ CLOCK INPUT The LPC47N2
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Note 1 : “Change” means either-
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1) Quiet (Active) Mode Any device m
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30 XNOR-CHAIN TEST MODE An XNOR-Cha
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31.2.2 CONFIGURATION SEQUENCE EXAMP
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HARD SOFT INDEX TYPE RESET RESET CO
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REGISTER ADDRESS DESCRIPTION PowerC
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LOGICAL DEVICE REGISTER ADDRESS DES
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LOGICAL DEVICE NUMBER LOGICAL DEVIC
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31.9.4 PARALLEL PORT SPP and EPP mo
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NAME REG INDEX DEFINITION FDD0 0xF4
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NAME IR Half Duplex Timeout Default
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PAR AM ETER SYM BOL M IN T YP M AX
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PAR AM ETER IOD 16 Type Bu ff er SY
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32.3 AC SPECIFICATIONS AC Test Cond
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33.2 LPC TIMING CLK Output Delay Tr
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33.3 FLOPPY DISK TIMING nDIR nSTEP
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nWRITE PD nDATASTB nADDRSTB nWAIT t
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33.5 ECP PARALLEL PORT TIMING Paral
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nALF PD nSTROBE BUSY t2 t1 t7 t8 t6
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33.6 SER IA L IRQ TIMIN G PCI_CLK S
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33.9 FAN AND FAN TACHOMETER TIMING
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PS2_CLK PS2_DAT PS2_EN PS2_T/R XMIT
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33.11 FLASH TIMING EFALE nEFRD EFAD
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FIGURE 102 - 208 PIN FL EX BGA 15.0
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INSTRUCTION DESCRIPTION BYTE COUNT
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INSTRUCTION DESCRIPTION BYTE COUNT
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The LPC47N252 adds a second data po
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Table 333 - CKCON Register - SFR 8E
Page 341 and 342:
TL2 The TL2 register (Table 340) is
Page 343 and 344:
Table 345 - Eicon Register Bit Desc
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SMSC LPC47N252 Data Sheet - Keil

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