SMSC LPC47N252 Data Sheet - Keil

LOGICAL DEVICE
NUMBER
0x06 RTC
LOGICAL
DEVICE FIXED / BASE OFFSETS NOTES
0x60, 0x61
Bank 0 Base address
+0 : Address Register
+1 : Data Register *
0x62, 0x63
0x07 KYBD
Bank 1 Base address
+0 : Address Register
+2 : Data Register *
0x60 : Data Register
0x64 : Command/Status Reg.
0x08 ACP1 EC +0 : Data Register
+1 : Command/Status Reg.
0x09 Mailbox Reg.
Interface
+0 : Index Register
+1 : Data Register.
0x0A LGPIO +0 : LGPIO Direction Register G
+1 : LGPIO Input Register G
+2 : LGPIO Output Register G
+3 : LGPIO Direction Register H
+4 : LGPIO Input Register H
+5 : LGPIO Output Register H
+6 : LGPIO Direction Register I
+7 : LGPIO Input Register I
+8 : LGPIO Output Register I
Note 1: Refer to the configuration register descriptions for setting the base address
4.1 HOST PROCESSOR INTERFACE (LPC)
The LPC47N252 communicates with the host over a Low Pin Count (LPC)interface. The LPC interface uses 3.3V
signaling. For electrical specifications see the Intel Low Pin Count Specification and the PCI Local Bus Specification,
Section 4.2.2. The following eight pins provide the LPC interface for the LPC47N252: LAD[3:0], LDRQ#, LPCPD#,
LFRAME#, LRESET#. (see Table 2 on page 15)
4.1.1 LPC BUS CYCLES DESCRIPTION
For a complete description of the LPC Bus Cycles see the Intel Low Pin Count Specification. This section provides
the specific tailoring of the Intel Low Pin Count Specification implemented in the LPC47N252.
LPC data transfers are serialized over a 4-bit bus, LAD[3:0]. The LAD[3:0] pins communicate the type, cycle direction,
chip selection, address, data, and wait states for each LPC Bus cycle. There is one control pin LFRAME# which is
used exclusively by the host to start or stop transfers. No peripherals drive this signal. Optionally implemented sideband
signals convey interrupts and power management features using the same signals found on current
motherboard implementations. The general flow of cycles is as follows (Table 6):
SMSC DS – LPC47N252 Page 26 Rev. 09/06/2000