SMSC LPC47N252 Data Sheet - Keil

16.2.1 Keyboard Data Write .......................................................................................................................... 195
16.2.2 Keyboard Data Read .......................................................................................................................... 195
16.2.3 Keyboard Command Write ................................................................................................................. 195
16.2.4 Keyboard Status Read........................................................................................................................ 195
16.3 8051-TO-HOST KEYBOARD COMMUNICATION................................................................................................... 195
16.4 HOST-TO 8051 KEYBOARD COMMUNICATION................................................................................................... 197
16.4.1 PCOBF Description ............................................................................................................................ 197
16.4.2 AUXOBF1 Description........................................................................................................................ 197
16.5 GATEA20 HARDWARE SPEED-UP ................................................................................................................. 198
16.5.1 8051 GATEA20 Control Registers...................................................................................................... 199
16.5.2 CPU_RESET Hardware Speed-Up .................................................................................................... 200
16.5.3 Port 92 ................................................................................................................................................ 201
16.5.4 GATEA20............................................................................................................................................ 202
16.6 DIRECT KEYBOARD SCAN............................................................................................................................... 203
16.7 EXTERNAL KEYBOARD AND MOUSE INTERFACE................................................................................ 203
17 PS/2 DEVICE INTERFACE............................................................................................................................ 204
17.1 SMSC PS/2 LOGIC OVERVIEW ...................................................................................................................... 204
17.2 PS/2 DATA FRAME........................................................................................................................................ 205
17.3 SMSC PS/2 MEMORY MAPPED CONTROL REGISTERS .................................................................................... 205
17.3.1 SMSC PS/2 Transmit Registers ......................................................................................................... 206
17.3.2 SMSC PS/2 Receive Registers .......................................................................................................... 206
17.3.3 SMSC PS/2 Control Registers............................................................................................................ 206
17.3.4 SMSC PS/2 Status Registers ............................................................................................................. 208
17.3.5 SMSC PS/2 Status_2 Registers ......................................................................................................... 210
17.4 DEVIL LOGIC OVERVIEW................................................................................................................................. 210
17.5 THE DEVIL PS/2 LOGIC COMMANDS................................................................................................................. 210
17.5.1 The Devil PS/2 logic Transmit Command........................................................................................... 210
17.5.2 The Devil PS/2 logic Receive Command............................................................................................ 211
17.5.3 The Devil PS/2 logic Inhibit Command ............................................................................................... 211
17.6 DEVIL PS/2 MEMORY MAPPED CONTROL REGISTERS ...................................................................................... 212
17.6.1 Devil PS/2 Control Registers .............................................................................................................. 212
17.6.2 Devil PS/2 Status Registers................................................................................................................ 213
17.6.3 Devil PS/2 Error Status....................................................................................................................... 214
17.6.4 Devil PS/2 Transmit Registers............................................................................................................ 214
17.6.5 Devil PS/2 Receive Registers............................................................................................................. 215
18 ACCESS.BUS ................................................................................................................................................ 216
18.1 OVERVIEW.................................................................................................................................................... 216
18.2 ACCESS.BUS REGISTER DESCRIPTIONS ........................................................................................................ 217
18.2.1 ACCESS.bus Control Register ........................................................................................................... 217
18.2.2 Access.bus Status Register................................................................................................................ 218
18.2.3 Own Address Register........................................................................................................................ 220
18.2.4 Data Register...................................................................................................................................... 220
18.2.5 Clock Register .................................................................................................................................... 221
18.2.6 ACCESS.BUS Switch Register........................................................................................................... 222
19 MAILBOX REGISTER INTERFACE .............................................................................................................. 223
19.1 OVERVIEW.................................................................................................................................................... 223
19.2 MAILBOX REGISTERS INTERFACE BASE ADDRESS............................................................................................. 224
19.3 MAILBOX REGISTERS INTERFACE ACCESS PORTS ............................................................................................ 224
19.4 MAILBOX REGISTERS ..................................................................................................................................... 224
19.5 THE SYSTEM/8051 INTERFACE REGISTERS .................................................................................................. 225
19.5.1 Mailbox Register 0: System-to-8051................................................................................................... 225
19.6 8051 STOP CLOCK REGISTER........................................................................................................................ 226
19.7 ESMI REGISTERS ..................................................................................................................................... 228
19.8 FDC SHADOW REGISTERS............................................................................................................................. 229
20 PULSE WIDTH MODULATORS .................................................................................................................... 231
20.1 OVERVIEW.................................................................................................................................................... 231
20.2 PWM SPEED CONTROL REGISTERS ............................................................................................................... 232
20.3 PWM CONTROL REGISTER............................................................................................................................ 233
21 FAN TACHOMETER INTERFACE ................................................................................................................ 236
SMSC DS – LPC47N252 Page 8 Rev. 09/06/2000