SMSC LPC47N252 Data Sheet - Keil

9.2.1 Vocabulary.......................................................................................................................................... 102
9.2.2 ECP Implementation Standard ........................................................................................................... 103
9.2.3 Description.......................................................................................................................................... 103
9.2.4 Register Definitions............................................................................................................................. 104
9.2.5 Operation............................................................................................................................................ 108
9.3 THE PARALLEL PORT PHYSICAL INTERFACE (PPPI).......................................................................................... 111
9.3.1 PPPI 8051 Mode................................................................................................................................. 112
9.3.2 PPPI Host (Legacy) Mode .................................................................................................................. 112
9.3.3 PPPI FDC Mode ................................................................................................................................. 112
9.3.4 FDC_nPP Pin Induced PPPI Modes Transitions................................................................................ 114
10 AUTO POWER MANAGEMENT.................................................................................................................... 116
10.1 SYSTEM POWER MANAGEMENT ...................................................................................................................... 116
10.2 DSR FROM POWERDOWN.............................................................................................................................. 116
10.3 WAKE UP FROM AUTO POWERDOWN .............................................................................................................. 116
10.4 REGISTER BEHAVIOR ..................................................................................................................................... 116
10.5 PIN BEHAVIOR............................................................................................................................................... 117
10.6 SYSTEM INTERFACE PINS............................................................................................................................... 117
10.7 FDD INTERFACE PINS ................................................................................................................................... 117
10.7.1 FDD Power Down Pin (FPD) Behavior............................................................................................... 118
10.8 UART POWER MANAGEMENT ........................................................................................................................ 119
10.9 EXIT AUTO POWERDOWN ............................................................................................................................... 119
10.10 PARALLEL PORT POWER MANAGEMENT....................................................................................................... 119
10.11 EXIT AUTO POWERDOWN ........................................................................................................................... 119
11 8051 EMBEDDED CONTROLLER ................................................................................................................ 120
11.1 8051 FUNCTIONAL OVERVIEW........................................................................................................................ 120
11.1.1 FEATURES......................................................................................................................................... 120
11.2 HIGH-PERFORMANCE 8051 IMPLEMENTED FEATURES ...................................................................................... 120
11.2.1 FUNCTIONAL BLOCKS ..................................................................................................................... 121
11.2.2 HIGH-PERFORMANCE 8051 CYCLE TIMING AND INSTRUCTION SET........................................ 121
11.3 POWERING UP OR RESETTING THE 8051 ......................................................................................................... 121
11.3.1 Default Reset Conditions.................................................................................................................... 121
11.4 CPU RESET SEQUENCE.............................................................................................................................. 123
11.5 8051 CLOCK CONTROLS................................................................................................................................ 123
11.5.1 Frequency Controls ............................................................................................................................ 123
11.6 8051 RING OSCILLATOR FAIL-SAFE CONTROLS.................................................................................. 125
11.7 8051 MEMORY MAP...................................................................................................................................... 126
11.8 8051 CONTROL REGISTERS........................................................................................................................... 126
11.8.1 Special Function Registers (SFRs)..................................................................................................... 126
11.8.2 Memory Mapped Control Register (MMCR) ....................................................................................... 127
11.8.3 8051 Configuration/Control Memory Mapped Registers..................................................................... 132
11.8.4 LED Controls ...................................................................................................................................... 135
11.9 8051 INTERRUPTS......................................................................................................................................... 136
11.9.1 8051 Internal Parallel Interrupts.......................................................................................................... 136
11.9.2 8051 INT0 Source Register ................................................................................................................ 138
11.9.3 8051 INT0 Mask Register................................................................................................................... 139
11.9.4 8051 INT1 Source Register ................................................................................................................ 139
11.9.5 8051 INT1 Mask Register................................................................................................................... 139
11.9.6 8051 Wakeup Source Registers......................................................................................................... 140
11.9.7 8051 Wakeup Mask Registers............................................................................................................ 143
11.9.8 8051 Hibernation Timer Register........................................................................................................ 145
11.9.9 8051 Edge Select Registers ............................................................................................................... 145
11.9.10 Power Fail IRQ ............................................................................................................................... 147
11.9.11 8051 External Serial IRQ Generation ............................................................................................. 148
11.10 8051 CODE DEBUGGING FEATURES ........................................................................................................... 149
11.10.1 External Flash Interface.................................................................................................................. 149
11.10.2 8051-controlled Parallel Port Interface ........................................................................................... 149
11.10.3 8051 Serial Port.............................................................................................................................. 149
11.10.4 8051 Single-Step Operation ........................................................................................................... 149
11.10.5 SFR GPIO Pins............................................................................................................................... 150
12 64K EMBEDDED FLASH ROM ..................................................................................................................... 151
12.1 OVERVIEW.................................................................................................................................................... 151
SMSC DS – LPC47N252 Page 6 Rev. 09/06/2000