SMSC LPC47N252 Data Sheet - Keil

Table 43 – FDC Status Register 2
B IT N O. SYM BOL N AM E D ESCR IPT ION
7 U nused. T his bi t is al ways "0" .
6 C M C ontr ol Mar k Any one of the fol low ing:
R ead D ata com mand - the F D C encountered a del eted data
address mar k.
R ead D el eted Data com mand - the F DC encounter ed a data
address mar k.
5 D D D ata Err or in
D ata F ield
T he F D C detected a C R C er r or i n the data fi el d.
4 W C W rong Cyli nder T he tr ack address fr om the sector ID fiel d is di fferent fr om the
track addr ess m aintai ned i nside the FD C.
3 U nused. T his bi t is al ways "0" .
2 U nused. T his bi t is al ways "0" .
1 BC Bad C yli nder T he tr ack address fr om the sector ID fiel d is di fferent fr om the
track addr ess m aintai ned i nside the FD C and i s equal to FF
hex, w hi ch indi cates a bad track wi th a har d err or accor di ng to
the IBM soft- sectored for m at.
0 M D M issi ng Data
Address Mar k
T he F D C cannot detect a data addr ess m ar k or a del eted data
address mar k.
Table 44 – FDC Status Register 3
B IT N O. SYM BOL N AM E D ESCR IPT ION
7 U nused. T his bi t is al ways "0" .
6 W P W ri te Pr otected Indicates the status of the WP pi n.
5 U nused. T his bi t is al ways "1" .
4 T 0 T rack 0 Indicates the status of the TR K0 pi n.
3 U nused. T his bi t is al ways "1" .
2 H D H ead Address Indicates the status of the HD SEL pi n.
1,0 D S1,0 D ri ve Select Indicates the status of the nD S1, nD S0 pi ns.
5.1 FDC RESET
There are three sources of system reset on the FDC:
The iRESET_OUT bit of the 8051’s Output Enable Register which controls the nRESET_OUT pin of the LPC47N252
(see section 11.8.3.5)
A reset generated via a bit in the DOR
A reset generated via a bit in the DSR.
At VCC2 power on, a VCC2 Power On Reset initializes the FDC. All resets take the FDC out of the power down
state.
All operations are terminated upon a RESET, and the Floppy Disk Controller enters an idle state. A reset while a disk
write is in progress will corrupt the data and CRC.
On exiting the reset state, various internal registers are cleared, including the Configure command information, and
the Floppy Disk Controller waits for a new command. Drive polling will start unless disabled by a new Configure
command.
nRESET_OUT Pin (Hardware Reset)
The nRESET_OUT pin is a global reset and clears all registers except those programmed by the Specify command.
The DOR reset bit is enabled and must be cleared by the host to exit the reset state.
SMSC DS – LPC47N252 Page 50 Rev. 09/06/2000