SMSC LPC47N252 Data Sheet - Keil

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VCC1_PWRGD VCC1 PWRGD VCC2 CLOCKI 1µs min. SMSC DS – LPC47N252 Page 24 Rev. 09/06/2000 3V 10µs min. FIGURE 4 - VCC2 POWER-UP TIMING 3V 3V FIGURE 5 - VCC1_PWRGD TIMING 1µs min.
4 FUNCTIONAL DESCRIPTION The host processor communicates with the LPC47N252 through a series of read/write registers. Register access is accomplished through programmed I/O or DMA transfers. All registers are 8 bits. The address map, shown below in Table 5, shows the set of operating registers and addresses for each of the logical blocks of the LPC47N252 Notebook I/O controller. The base addresses of all the blocks, except the Keyboard Controller can be moved via the configuration registers. LOGICAL DEVICE NUMBER Table 5 - LPC47N252 Operating Register Addresses LOGICAL DEVICE FIXED / BASE OFFSETS NOTES 0x00 FDC +0 : SRA +1 : SRB +2 : DOR +3 : TSR +4 : MSR/DSR +5 : FIFO +7 : DIR/CCR 0x03 Parallel Port 0x04 Serial Port 1 0x05 Infrared Port (UART) 0x60,0x61 0x05 IR-SCE 0x62,0x63 +0 : Data / ecpAfifo +1 : Status +2 : Control +400h : cfifo / ecpDfifo tfifo / cnfgA +401h : cnfgB +402h : ecr +0 : RB/TB ⎮ LSB div +1 : IER ⏐ MSB div +2 : IIR/FCR +3 : LCR +4 : MCR +5 : LSR +6 : MSR +7 : SCR +0 : RB/TB ⎮ LSB div +1 : IER ⏐ MSB div +2 : IIR/FCR +3 : LCR +4 : MCR +5 : LSR +6 : MSR +7 : SCR +0 : Register Block N, address 0 +1 : Register Block N, address 1 +2 : Register Block N, address 2 +3 : Register Block N, address 3 +4 : Register Block N, address 4 +5 : Register Block N, address 5 +6 : Register Block N, address 6 +7 : SCE Master Control Reg. SMSC DS – LPC47N252 Page 25 Rev. 09/06/2000
Page 1 and 2: _ Advanced Notebook I/O Controller
Page 3 and 4: GENERAL DESCRIPTION The LPC47N252 i
Page 5 and 6: 5.7.1 Read Data....................
Page 7 and 8: 12.2 FLASH MEMORY ARRAY ...........
Page 9 and 10: 21.1 FAN TACHOMETER OVERVIEW ......
Page 11 and 12: APPENDIX A: HIGH-PERFORMANCE 8051 C
Page 13 and 14: SMSC DS - LPC47N252 Page 13 Rev. 09
Page 15 and 16: 3 PIN FUNCTIONS TQFP PIN # FBGA NAM
Page 17 and 18: TQFP PIN NOTES NAME DESCRIPTION 44:
Page 19 and 20: TQFP PIN NOTES NAME DESCRIPTION 166
Page 21 and 22: Note 8: OUT0 and GPIO7 are suitable
Page 23: DEFAULT FUNCTION PWR ALTERNATE FUNC
Page 27 and 28: Table 6 - Basic Lpc Bus Cycle Descr
Page 29 and 30: 4.1.7.1 DMA Acknowledge The DMA ack
Page 31 and 32: 4.1.8.4 Sync Error Indication The p
Page 33 and 34: FIELD DRIVEN BY CLOCKS LAD[3:0] COM
Page 35 and 36: FIELD DRIVEN BY CLOCKS LAD[3:0] COM
Page 37 and 38: state (ACPI S1, APM POS), LPCPD# ma
Page 39 and 40: BIT 4 nTRACK 0 Active low status of
Page 41 and 42: BIT 3 READ DATA Active high status
Page 43 and 44: Enhanced Floppy Mode 2 (OS2) TAPE S
Page 45 and 46: 10 = 2 Meg Tape Note 1: The DRATE a
Page 47 and 48: BIT 0 - 6 UNDEFINED The data bus ou
Page 49 and 50: Table 41 - FDC Status Register 0 B
Page 51 and 52: DOR Reset vs. DSR Reset (Software R
Page 53 and 54: RQM and DIO must both equal "1" bef
Page 55 and 56: 5.6 FDC INSTRUCTION SET Table 46 -
Page 57 and 58: R EA D A T RA C K D AT A B US PHA S
Page 59 and 60: SPECIF Y D AT A B US PHA SE R /W D
Page 61 and 62: INVAL ID COD ES D AT A B US PHA SE
Page 63 and 64: SK BIT VAL UE 5.7.3 READ A TRACK Ta
Page 65 and 66: Table 52 - Verify Command Result Ph
Page 67 and 68: 5.8 FDC CONTROL COMMANDS Control co
Page 69 and 70: 0 1 .. E F 00 01 02 .. 7F 7F Table
Page 71 and 72: Gap2 field is expanded to a length
Page 73 and 74: MECHANISM FDC OUTPUT PINS STATE FDC
Page 75 and 76:
6 ACPI EMBEDDED CONTROLLER ACPI def
Page 77 and 78:
Once the host reads the data, the O
Page 79 and 80:
7 SERIAL PORT (UART) The LPC47N252
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7.1.5 INTERRUPT IDENTIFICATION REGI
Page 83 and 84:
Table 67 - Serial Character B IT 1
Page 85 and 86:
BIT 3 Framing Error (FE). Bit 3 ind
Page 87 and 88:
D ESIR ED B AU D R AT E D IVISOR US
Page 89 and 90:
7.3.1 EFFECT OF THE RESET ON REGIST
Page 91 and 92:
and the CPU starts to load it. When
Page 93 and 94:
8.1 IRRX/IRTX PIN ENABLE When MISC2
Page 95 and 96:
9 PARALLEL PORT The LPC47N252 incor
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BITS 1, 2 are not implemented as re
Page 99 and 100:
9.1.1.9.2 EPP 1.9 Write The timing
Page 101 and 102:
The chip drives the final sync and
Page 103 and 104:
The bit map of the Extended Paralle
Page 105 and 106:
Table 83 - Extended Control Registe
Page 107 and 108:
9.2.4.7 ister A) - ADDRESS OFFSET =
Page 109 and 110:
9.2.5.2 ECP Operation Prior to ECP
Page 111 and 112:
to 0. The ECP requests DMA transfer
Page 113 and 114:
9.3.3.1 PPPI FDC pin out The FDC si
Page 115 and 116:
Table 90 - FDC_nPP Initiated Pppi M
Page 117 and 118:
Accessing the LPC47N252 during powe
Page 119 and 120:
10.8 UART POWER MANAGEMENT Direct p
Page 121 and 122:
11.2.1 FUNCTIONAL BLOCKS Below are
Page 123 and 124:
System is running (Vcc2 and Vcc1 ar
Page 125 and 126:
KBDCLK[1:0] These 2 bits control th
Page 127 and 128:
FIX BIT REGISTERS SFR REGISTER NAME
Page 129 and 130:
MMCR REGISTER NAME SYSTEM ADDRESS S
Page 131 and 132:
MMCR REGISTER NAME SYSTEM ADDRESS S
Page 133 and 134:
11.8.3.3 Device ID Register By read
Page 135 and 136:
11.8.3.6 8051 LPC Bus Monitor The 8
Page 137 and 138:
IN4 IN5 GPIO0 GPIO1 GPIO2 IN6 GPIO7
Page 139 and 140:
11.9.3 8051 INT0 MASK REGISTER Tabl
Page 141 and 142:
RTC_ALRM asserted [D0] The RTC_ALRM
Page 143 and 144:
Table 118 - Wakeup Source Register
Page 145 and 146:
Table 125 - Wakeup Mask Register 7
Page 147 and 148:
Table 132 - Edge Select 5B HOST ADD
Page 149 and 150:
8051_IRQ ENABLE 8051_IRQ SELECT DES
Page 151 and 152:
12 64K EMBEDDED FLASH ROM 12.1 OVER
Page 153 and 154:
12.3 COMMAND SEQUENCE INTERFACE (CS
Page 155 and 156:
CMD CODE (hex) CSI MODE DESCRIPTION
Page 157 and 158:
12.3.6.1 Busy Bit - D7 The BUSY ind
Page 159 and 160:
12.3.7.2 Read Array Mode READ ARRAY
Page 161 and 162:
12.3.7.4 Page Erase Mode In Page Er
Page 163 and 164:
The CSI host interface and the Flas
Page 165 and 166:
Table 151 - 8051 Flash Boot Block P
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Declarations ERROR_MASK = 0x0070; /
Page 169 and 170:
13 FLASH PROGRAMMING INTERFACE 13.1
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FLASH PROGRAM REGISTER EXT FLASH (D
Page 173 and 174:
FPA[15:8] FPALE FPAD[7:0] nFPRD nFP
Page 175 and 176:
test vector FPA15:8 FPAD7:0 FPALE n
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EFALE nEFRD EFAD[7:0] EFA[15:8] t1
Page 179 and 180:
13.9 DEADMAN SWITCH 13.9.1 OVERVIEW
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13.9.4 DMS REGISTER T P FIGURE 42 -
Page 183 and 184:
13.10.3 EXT FLASH - D3 The EXT FLAS
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13.12 INTERNAL SCRATCH ROM The Kahu
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14.5 WDT MEMORY MAPPED REGISTERS Ta
Page 189 and 190:
15.1.1 EXITING IDLE MODE FIGURE 46
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15.3 WAKE-UP EVENTS N 8051 in sleep
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PIN WAKE-UP EVENTS GPIO11 WK_SE15 W
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16 KEYBOARD CONTROLLER 16.1 8042 ST
Page 197 and 198:
Table 177 - PCOBF HOST N/A 8051 0x7
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SA2 R/W D[0:7] IBF FLAG GATEA20 COM
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FE Command From KRESET Speed up Log
Page 203 and 204:
16.6 DIRECT KEYBOARD SCAN The LPC47
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6) When the controller is ready to
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PS2_T/R PS/2 Channel Transmit/Recei
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If the time from the 1st (start) bi
Page 211 and 212:
When sending a byte to a DEVIL PS/2
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17.6.2 DEVIL PS/2 STATUS REGISTERS
Page 215 and 216:
17.6.5 DEVIL PS/2 RECEIVE REGISTERS
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Table 195 - ACCESS.Bus Register Add
Page 219 and 220:
BIT 7 - PIN Pending Interrupt Not.
Page 221 and 222:
18.2.5 CLOCK REGISTER The Clock Reg
Page 223 and 224:
19 MAILBOX REGISTER INTERFACE 19.1
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19.5 THE SYSTEM/8051 INTERFACE REGI
Page 227 and 228:
System is fully powered & the 8051i
Page 229 and 230:
19.8 FDC SHADOW REGISTERS The LPC47
Page 231 and 232:
20 PULSE WIDTH MODULATORS 20.1 OVER
Page 233 and 234:
MAILBOX INDEX Table 218 - PWM1 Spee
Page 235 and 236:
PWM0 Clock Multiplier, D2 The PWM0
Page 237 and 238:
FAN1 and FAN2 Read Latch registers
Page 239 and 240:
21.5 FAN2 READ LATCH REGISTER The F
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22 8051 CONTROLLED PARALLEL PORT To
Page 243 and 244:
23 HOST CONTROLLED IR PORT It is po
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ITEM TYPE PIN NAMES WAKE CAPABLE BU
Page 247 and 248:
Table 230 - GPIO Input Register A H
Page 249 and 250:
Table 238 -Out Register D HOST ADDR
Page 251 and 252:
24.4.1 LPC LGPIO BASE ADDRESS Logic
Page 253 and 254:
Table 247 - LPC LGPIO Direction Reg
Page 255 and 256:
8051 MMCR ADDRESS REGISTER TYPE 805
Page 257 and 258:
24.4.3.3 8051 LGPIO Group I Registe
Page 259 and 260:
Table 266 - GPIO Buffer Type Config
Page 261 and 262:
24.6 GPIO PASS-THROUGH PORTS The LP
Page 263 and 264:
25 MULTIFUNCTION PIN 25.1 OVERVIEW
Page 265 and 266:
MISC[3,1] - D3 and D1 The MISC3 bit
Page 267 and 268:
Table 286 - Misc14 And Misc13 Bits
Page 269 and 270:
driven open-drain, and the Serial I
Page 271 and 272:
Block base address must be located
Page 273 and 274:
26.5.4 POWER MANAGEMENT 1 ENABLE RE
Page 275 and 276:
27 REAL TIME CLOCK 27.1 GENERAL DES
Page 277 and 278:
The 12/24 bit in Register B establi
Page 279 and 280:
27.7.2 REGISTER B RATE SELECT 32.76
Page 281 and 282:
27.7.6 GENERAL PURPOSE Registers 0x
Page 283 and 284:
27.10 32KHZ CLOCK INPUT The LPC47N2
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Note 1 : “Change” means either-
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1) Quiet (Active) Mode Any device m
Page 289 and 290:
30 XNOR-CHAIN TEST MODE An XNOR-Cha
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31.2.2 CONFIGURATION SEQUENCE EXAMP
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HARD SOFT INDEX TYPE RESET RESET CO
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REGISTER ADDRESS DESCRIPTION PowerC
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LOGICAL DEVICE REGISTER ADDRESS DES
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LOGICAL DEVICE NUMBER LOGICAL DEVIC
Page 301 and 302:
31.9.4 PARALLEL PORT SPP and EPP mo
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NAME REG INDEX DEFINITION FDD0 0xF4
Page 305 and 306:
NAME IR Half Duplex Timeout Default
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PAR AM ETER SYM BOL M IN T YP M AX
Page 309 and 310:
PAR AM ETER IOD 16 Type Bu ff er SY
Page 311 and 312:
32.3 AC SPECIFICATIONS AC Test Cond
Page 313 and 314:
33.2 LPC TIMING CLK Output Delay Tr
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33.3 FLOPPY DISK TIMING nDIR nSTEP
Page 317 and 318:
nWRITE PD nDATASTB nADDRSTB nWAIT t
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33.5 ECP PARALLEL PORT TIMING Paral
Page 321 and 322:
nALF PD nSTROBE BUSY t2 t1 t7 t8 t6
Page 323 and 324:
33.6 SER IA L IRQ TIMIN G PCI_CLK S
Page 325 and 326:
33.9 FAN AND FAN TACHOMETER TIMING
Page 327 and 328:
PS2_CLK PS2_DAT PS2_EN PS2_T/R XMIT
Page 329 and 330:
33.11 FLASH TIMING EFALE nEFRD EFAD
Page 331 and 332:
FIGURE 102 - 208 PIN FL EX BGA 15.0
Page 333 and 334:
INSTRUCTION DESCRIPTION BYTE COUNT
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INSTRUCTION DESCRIPTION BYTE COUNT
Page 337 and 338:
The LPC47N252 adds a second data po
Page 339 and 340:
Table 333 - CKCON Register - SFR 8E
Page 341 and 342:
TL2 The TL2 register (Table 340) is
Page 343 and 344:
Table 345 - Eicon Register Bit Desc
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SMSC LPC47N252 Data Sheet - Keil

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