SMSC LPC47N252 Data Sheet - Keil

Fast IR: Flush at end of frame.
4.1.7.5 DMA Arbitration
The peripheral does not have to arbitrate internally, even though it supports more than one DMA channel. When
more than one device requests service, send one request out, then the other.
Arbitration for DMA channels is performed through the 8237 within the host. Once the host has won arbitration on
behalf of a DMA channel. it asserts LFRAME# on the LPC bus and begins the DMA transfer.
4.1.7.6 DMA Transfer Types
The DMA protocol is used for all DMA transfer types, including single transfer mode, demand mode and verify mode.
For demand mode, the serialized requests will be back-to-back. For verify mode transfers, the peripheral should
drive data during the appropriate clocks; however, the host may ignore the values.
A verify transfer is similar to a DMA write, where the peripheral is transferring data to main memory. The indication
from the host is the same as a DMA write, so the peripheral will be driving data onto the LPC interface. However, the
host will not transfer this data into main memory. The LPC interface also supports increment mode.
The LPC interface does not support DMA channels being used on cascade mode (for emulating ISA masters). The
LPC interface does not support clock or decrement mode.
Channels 0-3 are 8 bit channels. Channels 5-7 are 16 bit channels (16 bit DMA channels are not supported in the
LPC47N252).
4.1.8 SYNC PROTOCOL
See the Intel Low Pin Count Specification Section 4.2.1.8 for a table of valid SYNC values.
4.1.8.1 Typical SYNC Usage
The SYNC pattern is used to add wait states. For read cycles, the peripheral must immediately drive the SYNC
pattern upon recognizing the cycle. The host immediately drives the sync pattern for write cycles. If the peripheral
needs to assert wait states, it does so by driving 0101 or 0110 on LAD[3:0] until it is ready, at which point it will drive
0000 or 1001. On any particular access, the peripheral must choose to assert 0101 or 0110, but not switch between
the two patterns.
The data will immediately follow the 0000 or 1001 value. If no wait states are needed, the peripheral can just drive
0000 or 1001 followed by the data. Because the SYNC pattern of 0000 or 1001 is always required, there is effectively
a minimum of 1 wait state for accesses.
The SYNC value of 0101 is used for normal wait states, wherein the cycle will complete within a few clocks.
The SYNC value of 0110 is used where the number of wait states is large. This is used for EPP cycles, where the
number of wait states could be quite large (>1 microsecond).
The SYNC value must be driven within 3 clocks.
4.1.8.2 SYNC Timeout
The SYNC value must be driven within 3 clocks. If the host observes 3 consecutive clocks without a valid SYNC
pattern, it will abort the cycle. The peripheral must not assume any particular timeout. When the host is driving
SYNC, it may have to insert a very large number of wait states, depending on PCI latencies and retries.
4.1.8.3 Sync Patterns and Maximum Number of Syncs
If the SYNC pattern is 0101, then the host assumes that the maximum number of SYNCs is 8.
If the SYNC pattern is 0110, then no maximum number of SYNCs is assumed. The peripheral must have protection
mechanisms to complete the cycle. This should only be used for EPP data transfers and should utilize the same
timeout protection that is in EPP.
SMSC DS – LPC47N252 Page 30 Rev. 09/06/2000