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Enabler II-G Assiste GPS Integration Guide - Farnell

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Enfora <strong>Enabler</strong> <strong>II</strong>I-G<br />

Modem <strong>Integration</strong> <strong>Guide</strong><br />

Figure 17 - Power Control Signal (using external processor) shows a typical connection from an external<br />

processor to the Enfora <strong>Enabler</strong> <strong>II</strong>I-G module, using the external PWR_CTL signal. The Enfora <strong>Enabler</strong> <strong>II</strong>I-G<br />

can be powered on by using the PWR_CTL signal, and reset with the RESET signal. When using PWR_CTL,<br />

the I/O or serial lines can be at any voltage state desired. It is recommended that the I/O and serial lines be tristated<br />

or set low when the GSM0308 is shutdown for an extended period of time to prevent any leakage current<br />

from the processor to the modem.<br />

CPU<br />

Open drain, or Tri-State I/O<br />

Open drain, or Tri-State I/O<br />

VBAT<br />

GPIO<br />

SERIAL<br />

PWR_CTL<br />

RESET<br />

Modem<br />

Figure 17 - Power Control Signal (using external processor)<br />

Parameter Parameter/Conditions MIN TYP MAX UNIT<br />

VIL Input Voltage – Low or float 0.3 x VBAT Vdc<br />

VIH Input Voltage – High 0.7 x VBAT 1.95 Vdc<br />

IPU Internal Pull-Up Resistor -40 -31 -15 μA<br />

<strong>II</strong>L Current sink -2.0 mA<br />

ON Pulse Duration 10 50 mS<br />

OFF Pulse Duration Minimum is programmable 10-250 100 5000 mS<br />

(AT$OFFDLY)<br />

Boot time Time to boot from power on<br />

to command prompt<br />

1.1 Sec<br />

GSM0308PB001 40 Version 1.03– 7/17/2007

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