Enabler II-G Assiste GPS Integration Guide - Farnell

Enfora Enabler III-G
Modem Integration Guide
6.6.12. I2C (Pins 48, 50)
Pin Name Pin Number Signal Direction Description
I2C_SCL 48 I/O I 2 C interface Master serial clock
I2C_SDA 50 I/O I 2 C interface Serial bi-directional data
The multi-master I 2 C peripheral provides an interface between a local host (LH) such as an MPU
processor and any I 2 C -bus-compatible device that connects via the I 2 C serial bus. External components
attached to the I 2 C bus can serially transmit/receive up to 8-bit data to/from the LH device through the
two-wire I 2 C interface.
2 2
This I C peripheral supports any slave or master I C -compatible device. The I 2 C bus is a multi-master
bus. The I 2 C controller supports the multi-master mode that allows more than one device capable of
controlling the bus to be connected to it. Each I 2 C device, including the on board processor, is
recognized by a unique address and can operate as either transmitter or receiver, according to the
function of the device. In addition to being a transmitter or receiver, a device connected to the I 2 C bus
can also be considered as master or slave when performing data transfers. Note that a master device is
the device which initiates a data transfer on the bus and generates the clock signals to permit that
transfer. During the transfer, any device addressed by this master is considered a slave.
For hardware reference only. There is no generic firmware to support this function.
Firmware must be added to enable I 2 C
I 2 C Parameter/Conditions Min Typ Max Units
VIH High level input voltage 1.26 1.8 1.9 V
VIL Low level input voltage 0 0.54 V
II Input leakage current ±1 μA
VOH High level output voltage, IO = 3 mA 1.44 1.8 V
VOL Low level output voltage, IO = 3 mA 0 0.36 V
Iz Leakage current ± 20 μA
I2Cfreq
Operating Frequency I2C_SCL, ‘Standard
100 KHz
I2Cfreq
Mode’
Operating Frequency I2C_SCL, ‘Standard
Mode’
400 KHz
GSM0308PB001 51 Version 1.03– 7/17/2007