TECHNICAL NOTES ON THE EEC-IV MCU - Auto diagnostics
TECHNICAL NOTES ON THE EEC-IV MCU - Auto diagnostics
TECHNICAL NOTES ON THE EEC-IV MCU - Auto diagnostics
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FC CLRVT CLRVT clear overflow trap same<br />
FD NOP BANK 3 NOP 8096/8061 different<br />
FE PREFIX SIGND/ALT changes multiply/divide to signed rename<br />
FF RST NOP system reset in 8096 NOP in 8061/5 different<br />
Eectch98-Part1.fm<br />
OP-CODE 8096 8061/5 DESCRIPTI<strong>ON</strong> DIFFERENCE<br />
Table 10: 8096-8061 Op-Codes<br />
The bank selection opcodes are 8065 -- as that is the difference between them, memory<br />
bank selection capabilities.<br />
00 10 20 30 40 50 60 70<br />
00 SKP ROMBANK* SJMP JNB0 AN3W d AN3B d AN2W d AN2B d<br />
01 CLRW CLRB SJMP JNB1 AN3W = ANDB = AN2W = AN2B =<br />
02 CPLW CPLB SJMP JNB2 AN3W @ AN3B @ AN2W @ AN2B @<br />
03 NEGW NEGB SJMP JNB3 ANEW () AN3B () AN2W () AN2B ()<br />
04 (ua) (ua) SJMP JNB4 AD3W d AD3B d AD2W d AD2B d<br />
05 DECW DECB SJMP JNB5 AD3W = AD3B = AD2W = AD2B =<br />
06 SEXW SEXB SJMP JNB6 AD3W @ AD3B @ AD2W @ AD2B @<br />
07 INCW INCB SJMP JNB7 AD3W () AD3B () AD2W () AD2B ()<br />
08 SHRW SHRB SCALL JB0 SBEW d SB3B d SB2W d SB2B d<br />
09 SHLW SHLB SCALL JB1 SB3W = SB3B = SB2W = SB2B =<br />
0A ASRW ASRB SCALL JB2 SB3W @ SB3B @ SB2W @ SB2B @<br />
0B (ua) (ua) SCALL JB3 SB3W () SB3B () SB2W () SB2B ()<br />
0C SHRDW (ua) SCALL JB4 ML3W d ML3B d ML2W d ML2B d<br />
0D SHLDW (ua) SCALL JB5 ML3W = ML3B = ML2W = ML2B =<br />
0E ASRDW (ua) SCALL JB6 ML3W @ ML3B @ ML2W @ ML2B @<br />
0F NORM (ua) SCALL JB7 ML3W () ML3B () ML2W () ML2B ()<br />
Table 11: Op-Code Map 00-70<br />
80 90 A0 B0 C0 D0 E0 F0<br />
00 ORRW d ORRB d LDW d LDB d STW d JNST DJNZ RET<br />
01 ORRW = ORRB = LDW = LDB = (ua) JLEU (ua) RETI/RETEI*<br />
02 ORRW @ ORRB @ LDW @ LDB @ STW @ JGT (ua) PUSHP<br />
03 ORRW () ORRB () LDW () LDB () STW () JNC (ua) POPP<br />
04 XRW d XRB d ADCW d ADCB d STB d JNVT (ua) BANK0*<br />
05 XRW = XRB = ADCW = ADCB = (ua) JNV (ua) BANK1*<br />
06 XRW @ XRB @ ADCW @ ADCB @ STB @ JGE (ua) BANK2*<br />
07 XRW () XRB () ADCW () ADCB () STB () JNE JUMP INT**<br />
08 CMPW d CMPB d SBBW d SBBB d PUSHW d JST (ua) CLC<br />
09 CMPW = CMPB = SBBW = SBBB = PUSHW = JGTU (ua) STC<br />
0A CMPW @ CMPB @ SBBW @ SBBB @ PUSHW @ JLE (ua) DI<br />
0B CMPW () CMPB () SBBW () SBBB () PUSHW () JLC (ua) EI<br />
0C D<strong>IV</strong>W d D<strong>IV</strong>B d LDZBW d LDSBW d POPW d JVT (ua) CLRVT<br />
0D D<strong>IV</strong>W = D<strong>IV</strong>B = LDZBW = LDSBW = (ua) JV (ua) BANK3*<br />
0E D<strong>IV</strong>W @ D<strong>IV</strong>B @ LDZBW @ LDSBW @ POPW @ JLT (ua) ALT*/SIGND/S<br />
0F D<strong>IV</strong>W () D<strong>IV</strong>B () LDZBW () LDSBW () POPW () JE (ua) NOP<br />
Table 12: Op-Code Map 80-FF<br />
Priority: Interrupt 16-Bit Address<br />
Highest High-Speed Input #0 0x201E<br />
Table 13: 8061 Interrupt Vectors and Priorities<br />
<strong>EEC</strong>-<strong>IV</strong> Technical Notes: Hardware 17 last edited: 9/29/98