Video and Image Processing Up Conversion Example Design

More documents

Recommendations

Info

Video and Image Processing Up Conversion Example Design If the FIFO becomes empty, then the interface will not assert valid and the rest of the system will wait. The FIFO should never become full - if this were to happen then data from the video data capture block would be lost and unpleasant visual artefacts would result. The TVP5146 video decoder chip on the Video Input Daughtercard performs analog-to-digital conversion of the video input signals and needs to be configured before it can be used. An I 2 C interface is provided for this purpose. The I 2 C Controller is an Avalon-MM slave which, when controlled by an Avalon-MM master, performs I2C reads and writes on an external bus as requested by that master. The Example Design Controller is an Avalon-MM master which directs the OpenCores I 2 C Controller to perform the necessary start-up sequence for the TI5146 chip, and then sends a signal to the NTSC Composite Input block telling it to start inputting data. The NTSC Composite Input block provides an Avalon-MM slave port for this purpose. The slave port has one register, one bit of which is significant: The least significant bit is a GO bit - when this is logic '1' the NTSC Composite Input block tries to input data, when it is logic '0' the NTSC Composite Input block does nothing. The I 2 C master is written in VHDL which can be found in the directory \altera_avalon_i2c. The example design controller VHDL can be found in \example_design_controller. Video Up Conversion Figure 7. Video Up Conversion Data Path Block Diagram 640 x 480 Interlaced 60 Hz YCbCr 4:2:2 8 Deinterlacer MegaCore Figure 7 shows a block diagram of the video up conversion data path subsystem. 640 x 480 Progressive 30 Hz YCbCr 4:2:2 Chroma Resampler MegaCore 640 x 480 Progressive 30 Hz YCbCr 4:4:4 Color Space Converter MegaCore Two Avalon-MM master interfaces 640 x 480 Progressive 30 Hz RGB Scaler MegaCore 1024 x 768 Progressive 30 Hz RGB 10 Altera Corporation Preliminary 8 Ready Valid Data
Figure 8. Data Stream Adapter Block Diagram Functional Description The video up conversion data path performs all of the video processing required to convert from an NTSC format input to a 1024×768 VGA output. It is composed entirely of Altera Video and Image Processing MegaCore functions and is assembled in DSP Builder, where it can be simulated independently of the rest of the system (see “Simulate the Data Path Component in DSP Builder” on page 30). The entire data path is exported from DSP Builder as a single SOPC Builder component, with standard Avalon-ST input and output interfaces and two Avalon-MM master ports. The data path makes use of four MegaCore functions connected in sequence to perform conversion. First a Deinterlacer converts from 60 Hz interlaced to 30 Hz progressive. Next a Chroma Resampler interpolates to convert from 4:2:2 subsampled color data to full 4:4:4 color data. This is followed by a Color Space Converter which transforms between the YCbCr and RGB color spaces. Finally a Scaler scales the 640×480 input image up to 1024×768 using bicubic interpolation. Timing and Data Format Adapters The next set of components in the data path is a set of adapters. The video up conversion subsystem processes an 8-bit wide data stream, one color plane every sample, but the frame buffer expects a 24-bit wide data stream, one pixel every sample. An Avalon-ST Data Format Adapter SOPC Builder block is used to transform the incoming 1×8-bit stream, into a 3×8-bit stream. The Avalon- ST Data Format Adapter block is a ready-latency 0 block whereas the rest of the data path is built with ready-latency 1 components. The Avalon-ST Data Format Adapter block is therefore connected using two Avalon-ST Timing Adapter blocks that convert between the ready-latency 1 stream and ready-latency 0 streams as shown in Figure 8. Ready Ready Ready Ready Avalon-ST Avalon-ST Avalon-ST Valid Valid Valid Valid Timing Data Format Timing Data Data Data Data Adapter Adapter Adapter 8 8 24 24 ready-latency 1 rules ready-latency 0 rules ready-latency 0 rules ready-latency 1 rules Altera Corporation 11 Preliminary
Page 1 and 2: October 2007, ver 4.0 Introduction
Page 3 and 4: Installing the Example Design Insta
Page 5 and 6: Figure 2. Single Video Channel Inpu
Page 7 and 8: Figure 4. System with Different Vid
Page 9: NTSC Video Input Figure 6. NTSC Vid
Page 13 and 14: Functional Description The external
Page 15 and 16: Hardware Requirements System Requir
Page 17 and 18: Review and Simulate the Example Des
Page 19 and 20: Figure 14. Video Source Block Revie
Page 25 and 26: Figure 23. Chroma Resampler Block R
Page 33 and 34: Figure 35. Avalon-MM Master Interfa
Page 35 and 36: Review the System Integration Using
Page 41 and 42: Set Up the Hardware and Configure t
Page 43 and 44: Conclusion Conclusion The Video and
Page 45: 101 Innovation Drive San Jose, CA 9

Video and Image Processing Up Conversion Example Design

Create successful ePaper yourself

Delete template?

Save as template?