Video and Image Processing Up Conversion Example Design

More documents

Recommendations

Info

Video and Image Processing Up Conversion Example Design The External RAM block is for simulation only, and is not synthesizable. The connection of the Deinterlacer to the external DDR2 memory is performed in SOPC Builder. The data and control interface's port blocks define the synthesizable boundary of the data path design that will interface to other system components in SOPC Builder. A description of your model is written out as a .mdlxml file when you run Signal Compiler. f Refer to these DSP Builder User Guide for information about compiling your design. A full compilation is not strictly necessary for integration of the design within SOPC Builder. You can alternatively use the DSPBuilder command alt_dspbuilder_mdl2xml to write the .mdlxml file by performing the following steps: 1. Save your example_design_data_path.mdl model file 2. At the MATLAB prompt, type the command: alt_dspbuilder_mdl2xml(gcs) Review the Final System using SOPC Builder In this section, you will review the Video and Image Processing Up Conversion example design using SOPC Builder, analyzing the individual modules that make up the system in the Quartus II software. The final system includes the following modules: ■ Example Design Controller ■ OpenCores I 2 C Master ■ NTSC Composite Input ■ Example Design Data Path (DSP Builder design) ■ Timing and Data Format Adapters ■ Frame Buffer ■ VGA Output ■ Pipeline Bridges ■ DDR2 SDRAM Controller 34 Altera Corporation Preliminary
Review the System Integration Using SOPC Builder To review the Quartus II project that describes the up conversion system, perform the following steps: 1. Run the Quartus II design software by choosing Quartus II 7.2 from the Programs section of the Windows Start menu. 2. Choose Open Project from the File menu. Browse to the directory where you installed the Video_IP_Example_Design and select the Video_IP_Example_Design.qpf file. (This file contains project definitions for the video up conversion example design.) 3. Choose Open from the File menu in the Quartus II software and select the file Video_IP_Example_Design.bdf. Click on Open to display this top-level file as shown in Figure 36. Figure 36. Top Level Video_IP_Example_Design.bdf file in Quartus II 4. In the Quartus II software, confirm that the Quartus II Fitter Physical Synthesis options are enabled (Assignments -> Settings -> Fitter Settings -> Physical Synthesis Optimizations) and the Physical Synthesis Effort is set to Extra. This is required to meet the system timing requirements. 5. Choose SOPC Builder from the Tools menu. Altera Corporation 35 Preliminary
Page 1 and 2: October 2007, ver 4.0 Introduction
Page 3 and 4: Installing the Example Design Insta
Page 5 and 6: Figure 2. Single Video Channel Inpu
Page 7 and 8: Figure 4. System with Different Vid
Page 9 and 10: NTSC Video Input Figure 6. NTSC Vid
Page 11 and 12: Figure 8. Data Stream Adapter Block
Page 13 and 14: Functional Description The external
Page 15 and 16: Hardware Requirements System Requir
Page 17 and 18: Review and Simulate the Example Des
Page 19 and 20: Figure 14. Video Source Block Revie
Page 25 and 26: Figure 23. Chroma Resampler Block R
Page 33: Figure 35. Avalon-MM Master Interfa
Page 37 and 38: Review the System Integration Using
Page 39 and 40: Review the System Integration Using
Page 41 and 42: Set Up the Hardware and Configure t
Page 43 and 44: Conclusion Conclusion The Video and
Page 45: 101 Innovation Drive San Jose, CA 9

Video and Image Processing Up Conversion Example Design

Create successful ePaper yourself

Delete template?

Save as template?