Video and Image Processing Up Conversion Example Design

Video and Image Processing Up Conversion Example Design
Frame Buffer Component
Figure 9 shows a simple block diagram of the Frame Buffer component
and its connections to external RAM via SOPC Builder.
Figure 9. Frame Buffer Component Block Diagram
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The Frame Buffer block is a beta version of a new Video and Image
Processing Suite MegaCore function which can be found in the directory
\frame_buffer_beta.
The purpose of this block is to provide a triple buffering function which
allows the input and output sides to run asynchronously and at different
frame rates. In the example design, this is necessary because the output of
the video data path is 1024×768 progressive video @ 30 fps, but the VGA
output cannot run slower than 60 fps.
The Frame Buffer block inputs and outputs flow-controlled streams of
video data over standard interfaces of the type described in “Data and
Flow Control Signals” on page 18.
The input and output data interfaces have 24-bit wide data ports and
output all three color planes in parallel, with blue on the least significant
bits and red on the most significant bits. This makes the output interface
compatible with the input interface on the VGA Output block.
The block uses three equal-sized frame buffers stored in external memory.
The base address of this memory in the Avalon-MM address space is set
at 0x10000000. There must be 8MByte of free memory at this address.
12 Altera Corporation
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