Video and Image Processing Up Conversion Example Design

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Video and Image Processing Up Conversion Example Design Figure 41. Quartus II Physical Synthesis Assignments Quartus II Compilation fails to meet F Max of 130MHz Ensure that the physical synthesis effort (Assignments -> Settings -> Fitter Settings -> Physical Synthesis Optimizations) is set to Extra in the Quartus II software as shown in Figure 41. 44 Altera Corporation Preliminary
101 Innovation Drive San Jose, CA 95134 www.altera.com Literature Services: literature@altera.com Revision History Revision History Table 1 shows the revision history for the AN-427: Video and Image Processing Up Conversion Example Design application note. Table 1. AN-427 Revision History Version Date Errata Summary 4.0 October 2007 Updated for Quartus version 7.2. The design now uses DSP Builder Video Source and Video Sink blocks and the triple buffer block has been replaced by a Frame Buffer MegaCore function. Removed obsolete troubleshooting issue “Compilation Fails in Analysis and Synthesis”. 3.0 May 2007 Updated for Quartus version 7.1. 2.0 December 2006 Updated for Quartus version 6.1. 1.2 July 2006 Added troubleshooting issues “Compilation Fails in Analysis and Synthesis” and “DDR2 Fails in Analysis and Synthesis or In Timing Analysis”. 1.1 July 2006 Updated algorithm used by the triple buffer block, effects of VGA starvation, description of the image stream frame counter block, and other minor edits. 1.0 June 2006 First release of this application note. Copyright © 2007 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. Altera Corporation 45 Preliminary
Page 1 and 2: October 2007, ver 4.0 Introduction
Page 3 and 4: Installing the Example Design Insta
Page 5 and 6: Figure 2. Single Video Channel Inpu
Page 7 and 8: Figure 4. System with Different Vid
Page 9 and 10: NTSC Video Input Figure 6. NTSC Vid
Page 11 and 12: Figure 8. Data Stream Adapter Block
Page 13 and 14: Functional Description The external
Page 15 and 16: Hardware Requirements System Requir
Page 17 and 18: Review and Simulate the Example Des
Page 19 and 20: Figure 14. Video Source Block Revie
Page 25 and 26: Figure 23. Chroma Resampler Block R
Page 33 and 34: Figure 35. Avalon-MM Master Interfa
Page 35 and 36: Review the System Integration Using
Page 41 and 42: Set Up the Hardware and Configure t
Page 43: Conclusion Conclusion The Video and

Video and Image Processing Up Conversion Example Design

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