Video and Image Processing Up Conversion Example Design

Functional Description
The external memory is a double data rate (DDR) RAM in the example
design, and is accessed via SOPC Builder arbitration logic as shown in
Figure 9. SOPC Builder is responsible for sharing access time to the DDR
between the frame buffer block and other blocks in the design. The block
includes a writer, which writes the input stream into one of the buffers,
and a reader, which reads the output stream from another (never the
same) buffer. There is always one buffer which is neither being written to
nor read from. This "spare" buffer is required to allow the input and
output to run at differing frame rates.
The frame buffer operates by swapping frames according to the following
algorithms.
Each time the input finishes writing a frame of data into a buffer:
Wait until the spare buffer has data that has already been displayed,
then start writing the next input frame into the spare buffer. The
buffer just written into then becomes the new spare buffer. No frame
is dropped in this configuration.
Each time the output finishes reading a frame of data from a buffer:
If the spare buffer has data which has not yet been displayed then
start reading the next output frame from the spare buffer. The frame
buffer just read from then becomes the new spare buffer. Otherwise,
start reading the next output frame from the same buffer (a frame is
repeated).
VGA Output
Figure 10 shows a simple block diagram of the VGA Output component.
Figure 10. VGA Output Component
Ready
Valid
Data
24
SOPC System Clock
(130 MHz)
Dual-Clock FIFO
VGA Clock
(65 MHz)
VGA Syncs
Generator
R
G
B
Syncs
The VGA Output is an SOPC Builder component written in Verilog HDL.
The source code can be found in the directory \vga_output.
Altera Corporation 13
Preliminary