Video and Image Processing Up Conversion Example Design

NTSC Video Input
Figure 6. NTSC Video Input Block Diagram
Y/C
Syncs
Functional Description
Figure 6 shows a simple block diagram of the three components of the
NTSC video input subsystem.
I 2 C
Controller
Video Data
Capture
Example
Design
Controller
Daughtercard Clock
(~25 MHz)
SOPC System Clock
(130 MHz)
Dual-Clock FIFO
NTSC Composite Input
The NTSC input into the system requires three SOPC Builder components
to work together: the I 2 C Controller, the Example Design Controller and
the NTSC Composite Input block. These are shown in Figure 6, with a
dotted line delineating each SOPC Builder component.
The NTSC Composite Input block operates similarly to its counterpart the
VGA Output block. It is written in VHDL which can be found in the
\ntsc_composite_input folder.
Video data in YCbCr 4:2:2 format and associated synchronization signals
are input into the Video Data Capture block from the Video Input
Daughtercard. This block identifies active video parts of the picture and
inserts just this data into the Dual-Clock FIFO. A standard flow controlled
interface on the output of the FIFO allows this data to be read by the next
part of the system (the video processing data path in the case of the
example design) at the system clock rate of 130 MHz.
Altera Corporation 9
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Data