Video and Image Processing Up Conversion Example Design

Review the System Integration Using SOPC Builder
Most of the parameters are self explanatory: The input resolution is
1024×768 with the RGB color samples streamed as 3×8-bits in parallel.
The triple buffering function is configured to repeat frames. This is
necessary because the VGA output cannot run slower than 60 fps and the
output of the upscaling video data path is progressive video @ 30 fps but
frame dropping is not necessary and is consequently not allowed. To
perform its function, the frame buffer uses 7.4Mbyte of memory at base
address 0x10000000.
The FIFO depth and burst target parameters configure the behavior of the
Memory Writer and Memory Reader components shown in Figure 9 on
page 12. To transmit and receive data to and from the memory in bursts,
the Reader and the Writer components each have a small FIFO to store
read and write data. The two FIFO depth parameters control the sizes of
these FIFOs.
Write requests from the Memory Writer are issued in sequence to the
SOPC Builder arbitration logic layer when the write master FIFO has
buffered at least as many words as specified by the burst target
parameter. The Memory Writer then keeps issuing write requests until its
FIFO is empty. The Memory Writer also starts a write burst when it
reaches the end of a line of pixels regardless of the number of data words
currently stored in the FIFO.
Read requests from the Memory Reader are issued when the read master
FIFO contains at least as many available spaces as specified by the burst
target parameter. Read requests that have been issued but have not yet
been fulfilled have a reserved place in the FIFO and do not count as
available space. The Memory Reader stops issuing read requests when
the FIFO is full, including pending read requests.
7. Click Cancel to close the Frame Buffer BETA block dialog box.
Two Avalon-MM Pipeline Bridge components are used between the
memory master interfaces of the Deinterlacer and Frame Buffer Megacore
functions and the DDR2 SDRAM Controller Megacore function.
8. Double-click on pipeline_bridge to open the parameterization
interface for the first Pipeline Bridge component (Figure 40 on
page 40).
9. Click Cancel to close the Avalon-MM Pipeline Bridge dialog box.
10. Double-click on pipeline_bridge_1 to open the parameterization
interface for the second Pipeline Bridge component.
Altera Corporation 39
Preliminary