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Video and Image Processing Up Conversion Example Design

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<strong>Video</strong> <strong>and</strong> <strong>Image</strong> <strong>Processing</strong> <strong>Up</strong> <strong>Conversion</strong> <strong>Example</strong> <strong>Design</strong><br />

Simulate the Data Path Component in DSP Builder<br />

The simulation of video systems is a computationally expensive task, <strong>and</strong><br />

can take several hours to perform a gate level simulation of a frame of<br />

high resolution video. However, DSP Builder can accelerate simulation of<br />

the <strong>Video</strong> <strong>and</strong> <strong>Image</strong> <strong>Processing</strong> Suite MegaCore functions (by a factor of<br />

approximately 30) using transaction level simulation.<br />

This increase opens the door to rapid prototyping <strong>and</strong> experimentation<br />

leading to higher image quality. This section describes how to simulate<br />

the design using both fast functional simulation <strong>and</strong> traditional cycle<br />

accurate simulation.<br />

For convenience, the example design contains pre-generated sample<br />

input <strong>and</strong> output video files in .avi format. The vip_car_out.avi file<br />

contains several frames of simulated video. To view the image input <strong>and</strong><br />

output files, open the .avi files in Windows Media Player.<br />

You can change a parameter for any of the MegaCore functions described<br />

in the previous section by double-clicking the appropriate block in DSP<br />

Builder to display the MegaWizard interface. The associated files are<br />

regenerated with the new parameters when you click Finish in the<br />

MegaWizard interface.<br />

Fast Functional Simulation<br />

The example model contains a Simulation Accelerator block. When this<br />

block displays Bit-accurate simulation (faster), all <strong>Video</strong> <strong>and</strong><br />

<strong>Image</strong> <strong>Processing</strong> Suite blocks are simulated at the transaction level,<br />

resulting in significant simulation acceleration compared to traditional<br />

cycle-accurate simulation (Figure 31).<br />

Figure 31. Simulation Accelerator Block set for Bit-Accurate Simulation<br />

f For more information about fast functional simulation, refer to the Using<br />

the Simulation Accelerator chapter in the DSP Builder User Guide.<br />

algebraic_loop_cut_dil Block<br />

This block is used to prevent Simulink from detecting an algebraic loop<br />

between the Deinterlacer <strong>and</strong> the two Avalon-MM master interfaces.<br />

30 Altera Corporation<br />

Preliminary

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