Video and Image Processing Up Conversion Example Design

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Video and Image Processing Up Conversion Example Design System Requirements A stream of video data is input into the block over a standard flow controlled interface. This interface includes a 24-bit wide data port because red, green, and blue data is input into the block in parallel, so that all of the data for a pixel can be input in a single clock cycle. The least significant eight bits form the blue channel, the green is in the middle and the most significant eight bits carry the red channel. The interface also includes ready and valid lines for flow control. f Refer to “Data and Flow Control Signals” on page 18 for details of the flow controlled interface. The video data is input via a flow controlled interface, so data is not transferred on every clock cycle, only those clock cycles where valid = '1', and the clock therefore need not be the same rate as the VGA output clock. The clock actually used at this end is therefore the SOPC System clock, which runs at 130MHz in the example design. Data is input into a dual-clock FIFO which provides clock domain crossing to the 65MHz VGA clock and also provides a queue where pixels can wait when the VGA output is in blanking and does not need pixel data. If this FIFO ever becomes full, then the flow controlled interface will indicate that the VGA output is not ready for data and earlier parts of the pipe will stop. The FIFO should never become empty while the system is running. If it does, then the situation could arise that there is no pixel data available when the VGA Syncs Generator needs it. In this case, the VGA output module will generate red pixels on its outputs (R:255, G:0, B:0) as an indication of data starvation. Synchronization and blanking signals for VGA running the standard video electronics standards association (VESA) 1024×768 resolution are calculated and output by the VGA Syncs Generator block. This block also pulls data out of the dual-clock FIFO and presents it on R, G, and B outputs when the syncs indicate the VGA should output active picture data. Signals from the VGA Syncs Generator form the output of the VGA Output block, and are wired directly to pins connected to the 2C35 board's VGA digital-to-analog converter (DAC) in the example design. This section describes the hardware and software requirements to run the video up conversion example design. 14 Altera Corporation Preliminary
Hardware Requirements System Requirements The video and image processing up conversion example design requires the following hardware components: ■ Cyclone II EP2C70 DSP Development Board. ■ NTSC video source with composite output. ● The example design has been verified using: An Apple Video iPod. (An Apple TV out cable is required to connect an Apple Video iPod to the composite input.) An IBM Thinkpad T41 laptop with ATI v8.133 drivers generating the NTSC video source. (A S-Video to phono cable, S-Video to RCA, or a S-Video lead -> SVHS-Phono Adapter -> phono lead connection is required to connect a Thinkpad T41 to the Altera Video Input Daughtercard composite input.) A Sony Handycam DCR HC-46 ● Other video sources outputting NTSC can be used including video cameras. ■ An Altera Video Input Daughtercard (with two separate input channels of composite input). ■ A monitor or display with a VGA connector supporting 1024×768 resolution. ■ A VGA cable to connect the Cyclone II VGA output to the monitor 1 The Cyclone II EP2C70 DSP Development Board, Video Input Daughtercard and reference design are included in the Altera Video Development Kit, Cyclone II Edition. Software Requirements The up conversion example design is supported on Windows XP only. Ensure that the software provided with the development kit is installed onto your PC. f For more information on the software installation, refer to the DSP Development Kit, Cyclone II Edition, Getting Started User Guide. You must have the following software installed on your PC: ■ Quartus II software, version 7.2 ■ MegaCore IP Library, version 7.2 ■ The MathWorks release R14 SP3, R2006a, R2006b, or R2007a ■ DSP Builder version 7.2 1 This application note assumes that you have installed the software into the default locations. Altera Corporation 15 Preliminary
Page 1 and 2: October 2007, ver 4.0 Introduction
Page 3 and 4: Installing the Example Design Insta
Page 5 and 6: Figure 2. Single Video Channel Inpu
Page 7 and 8: Figure 4. System with Different Vid
Page 9 and 10: NTSC Video Input Figure 6. NTSC Vid
Page 11 and 12: Figure 8. Data Stream Adapter Block
Page 13: Functional Description The external
Page 17 and 18: Review and Simulate the Example Des
Page 19 and 20: Figure 14. Video Source Block Revie
Page 25 and 26: Figure 23. Chroma Resampler Block R
Page 33 and 34: Figure 35. Avalon-MM Master Interfa
Page 35 and 36: Review the System Integration Using
Page 41 and 42: Set Up the Hardware and Configure t
Page 43 and 44: Conclusion Conclusion The Video and
Page 45: 101 Innovation Drive San Jose, CA 9

Video and Image Processing Up Conversion Example Design

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