Video and Image Processing Up Conversion Example Design

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Video and Image Processing Up Conversion Example Design 1 The DSP Builder up conversion subsystem could be built directly in SOPC Builder by wiring up MegaCore function blocks from the list of Video and Image Processing modules. However, DSP Builder is required to simulate the data path and perform early design verification. The custom hardware components: example_design_controller, ntsc_composite_input, openCores_I2c_master, and vga_output appear in the Video IP Example Design module list. The Frame Buffer BETA MegaCore function block is available in the list of Video and Image Processing modules. These components are described in the “Functional Description” on page 8. The Frame Buffer BETA block is added to the design and configured in SOPC Builder. 6. Click on the my_alt_vip_vfb instance in the SOPC Builder Module Name column to open the parameterization interface for the Frame Buffer BETA block (Figure 39). Figure 39. Parameters for the Frame Buffer MegaCore Function 38 Altera Corporation Preliminary
Review the System Integration Using SOPC Builder Most of the parameters are self explanatory: The input resolution is 1024×768 with the RGB color samples streamed as 3×8-bits in parallel. The triple buffering function is configured to repeat frames. This is necessary because the VGA output cannot run slower than 60 fps and the output of the upscaling video data path is progressive video @ 30 fps but frame dropping is not necessary and is consequently not allowed. To perform its function, the frame buffer uses 7.4Mbyte of memory at base address 0x10000000. The FIFO depth and burst target parameters configure the behavior of the Memory Writer and Memory Reader components shown in Figure 9 on page 12. To transmit and receive data to and from the memory in bursts, the Reader and the Writer components each have a small FIFO to store read and write data. The two FIFO depth parameters control the sizes of these FIFOs. Write requests from the Memory Writer are issued in sequence to the SOPC Builder arbitration logic layer when the write master FIFO has buffered at least as many words as specified by the burst target parameter. The Memory Writer then keeps issuing write requests until its FIFO is empty. The Memory Writer also starts a write burst when it reaches the end of a line of pixels regardless of the number of data words currently stored in the FIFO. Read requests from the Memory Reader are issued when the read master FIFO contains at least as many available spaces as specified by the burst target parameter. Read requests that have been issued but have not yet been fulfilled have a reserved place in the FIFO and do not count as available space. The Memory Reader stops issuing read requests when the FIFO is full, including pending read requests. 7. Click Cancel to close the Frame Buffer BETA block dialog box. Two Avalon-MM Pipeline Bridge components are used between the memory master interfaces of the Deinterlacer and Frame Buffer Megacore functions and the DDR2 SDRAM Controller Megacore function. 8. Double-click on pipeline_bridge to open the parameterization interface for the first Pipeline Bridge component (Figure 40 on page 40). 9. Click Cancel to close the Avalon-MM Pipeline Bridge dialog box. 10. Double-click on pipeline_bridge_1 to open the parameterization interface for the second Pipeline Bridge component. Altera Corporation 39 Preliminary
Page 1 and 2: October 2007, ver 4.0 Introduction
Page 3 and 4: Installing the Example Design Insta
Page 5 and 6: Figure 2. Single Video Channel Inpu
Page 7 and 8: Figure 4. System with Different Vid
Page 9 and 10: NTSC Video Input Figure 6. NTSC Vid
Page 11 and 12: Figure 8. Data Stream Adapter Block
Page 13 and 14: Functional Description The external
Page 15 and 16: Hardware Requirements System Requir
Page 17 and 18: Review and Simulate the Example Des
Page 19 and 20: Figure 14. Video Source Block Revie
Page 25 and 26: Figure 23. Chroma Resampler Block R
Page 33 and 34: Figure 35. Avalon-MM Master Interfa
Page 35 and 36: Review the System Integration Using
Page 37: Review the System Integration Using
Page 41 and 42: Set Up the Hardware and Configure t
Page 43 and 44: Conclusion Conclusion The Video and
Page 45: 101 Innovation Drive San Jose, CA 9

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