Video and Image Processing Up Conversion Example Design

Installing the
Example Design
Installing the Example Design
The example design files are included on the Video Development Kit,
Cyclone II Edition CD-ROM or can be downloaded as a zip file from the
Altera website.
Figure 1 shows the directory structure for the example design files when
they have been extracted from the zip file.
Figure 1. Example Design Directory Structure
Video_IP_Example_Design_
Contains top level block design file (Video_IP_Example_Design.bdf), Quartus II settings file
(Video_IP_Example_Design.qsf), Quartus II project file (Video_IP_Example_Design.qpf),
DSP Builder model file (example_design_data_path.mdl), SOPC Builder project file
(video_system_SOPC.sopc), and PLL files for the DDR2 Controller (ddr_pll_cycloneii*.*).
altera_avalon_i2c
Contains SOPC Builder components (_hw.tcl and VHDL files) for the
I 2 C controller that communicates with the digital composite input card.
example_design_controller
Contains SOPC Builder components (_hw.tcl and VHDL files) for the
Avalon master used by the I 2 C controller and NTSC composite input module.
frame_buffer_beta
Contains a beta version of the Frame Buffer MegaCore function. The frame buffer block
can perform a double or triple buffering function and is inserted between the other Video
and Image Processing Suite MegaCore functions and the VGA output.
ntsc_composite_input
Contains SOPC Builder components (_hw.tcl and VHDL files) which
decode the video signal from the digital composite input card.
vga_output
Contains SOPC Builder components (_hw.tcl and VHDL files) for the VGA
output driver.
docs
Contains this document (AN-427.pdf).
Notes to Figure 1:
(1) The Video_Ip_Example_Design_ directory also includes other files that
are included for convenience but can be regenerated using the tools described in
this application note.
(2) If you want to use the Frame Buffer MegaCore function in other designs, you can
copy the frame_buffer_beta directory to your Altera IP v7.2 installation directory
(C:\altera\72\ip by default). The Frame Buffer MegaCore function will then be
accessible in the Quartus II software using the MegaWizard Plug-In Manager or
from the System Contents tab in SOPC Builder.
The top level directory Video_IP_Example_Design_ contains a
Quartus II project file (Video_IP_Example_Design.qpf), DSP Builder
model file (example_design_data_path.mdl), and SOPC Builder project
file (video_system_sopc.sopc). These files can be opened to explore the
design as described in “Review and Simulate the Example Design” on
page 16.
Altera Corporation 3
Preliminary