Video and Image Processing Up Conversion Example Design

Review and Simulate the Example Design
The deinterlacer is parameterized to process an interleaved image of
resolution 640×480 pixels, with 2 color planes in sequence due to the 4:2:2
sampling rate of the interleaved input image. Weave deinterlacing is
applied in this example and requires a frame buffer stored in off-chip
memory so that lines from different fields can be woven together. For this
reason, the weave deinterlacer has a built in double-buffering function.
When in weave mode, the deinterlacer has two 64-bit Avalon-MM master
ports. These must be connected to an external memory with enough space
to store four full fields of video data.
The base address of frame buffers represents the address in the
Avalon-MM address space where the base of the frame buffer memory is
to be located and there must be at least 1.2MByte of free RAM at this
location. (7.4MByte is used by the frame buffer block at a base address of
0x10000000.)
8. Click Cancel to close the Deinterlacer MegaWizard page.
External Memory Simulation Block
The example design uses a DSP Builder Simulation-only block to allow
simulation of an external RAM memory. The memory model is designed
for use with the Altera Video and Image Processing MegaCore functions,
but can be used for other purposes.
Data can be written to (or read from) the RAM model via Avalon-MM
read and write master ports. In the example design, the RAM model is
connected to the Deinterlacer function.
1 Note that the external RAM model can be used for simulation
only and will not generate HDL if the design is compiled with
Signal Compiler.
Figure 21 shows the External RAM memory block in DSP Builder.
Figure 21. External RAM Memory Block
Altera Corporation 23
Preliminary