Burn-in & Test Socket Workshop - BiTS Workshop

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The New YieldPro Array Contactor • A new solution is needed for contacting new chip scale packages, such as BGA and LCC • Agilent’s new YieldPro Array design addresses technologies, Bluetooth®, Wireless LAN and high speed digital components • All are heading toward higher frequencies and require good performance in high speed digital, and at the 3rd harmonic of the RF fundamental Patent USP# 6,299,459 Julius Botka BITS.ppt 10/31/01 Page 5
Design Considerations Problem: Lack of reliable/repeatable contact between tester and component to be tested Solution: Slider • Two parallel contact paths from solder ball/contact pad to DUT board • Contacts do not wear the DUT board Julius Botka BITS.ppt 10/31/01 Page 6
Page 1 and 2: Burn-in & Test Socket Workshop IEEE
Page 3 and 4: Burn-in & Test Socket Workshop Tech
Page 5 and 6: Discussion Topics ▼ Modeling & it
Page 7 and 8: Designing Load Boards for Optimal P
Page 9 and 10: Load Board Effects ▼ Things to im
Page 11 and 12: Crosstalk Improvements ▼ Increase
Page 13 and 14: Load Board Pad Size and Placement 1
Page 15 and 16: Return Loss (dB) 0 -5 -10 -15 -20 -
Page 17 and 18: Model Validation & Performance Exam
Page 19 and 20: Model Validation & Performance Exam
Page 21 and 22: Return Loss (dB) 0 -5 -10 -15 -20 -
Page 23 and 24: Conclusion ▼ Modeling trends can
Page 25 and 26: Brief History • Semiconductor man
Page 27: Today’s evolution of the business
Page 31 and 32: Problem: Excessive and undefined co
Page 33 and 34: Problem: Damage to the bottom of th
Page 35 and 36: Problem: After 100,000 plunges, exc
Page 37 and 38: Problem: Plating will wear away, ox
Page 39 and 40: Problem: Usability issues revolving
Page 41 and 42: Coplanar waveguide substrate with g
Page 43 and 44: Fixture time domain is computed fro
Page 45 and 46: S 11 Gated, coplanar substrate elec
Page 47 and 48: Model of Contacts with Effects of H
Page 49 and 50: S 11 of contact region from model C
Page 51 and 52: Accounting for housing effects * *
Page 53 and 54: Economic Benefits: • Increase the
Page 55 and 56: Introduction This presentation summ
Page 57 and 58: Socket Requirements for Testing RF
Page 59 and 60: Qualification Process: Determine pa
Page 61 and 62: Qualification Process: Test Sockets
Page 63 and 64: Mechanical Analysis: Pogo-style soc
Page 65 and 66: Mechanical Analysis: S-contact sock
Page 67 and 68: Mechanical Analysis: Low-profile in
Page 69 and 70: Mechanical Analysis: Conductive ela
Page 71 and 72: Qualification Process: Test socket
Page 73 and 74: Qualification Process: Test socket
Page 75 and 76: Electrical Performance Simulations
Page 77 and 78: Electrical Performance Simulations
Page 79:
Recognition of Support John Blondi
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