Burn-in & Test Socket Workshop - BiTS Workshop

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COPYRIGHT NOTICE • The papers in this publication comprise the proceedings of the 2002 BiTS Workshop. They reflect the authors’ opinions and are reproduced as presented , without change. Their inclusion in this publication does not constitute an endorsement by the BiTS Workshop, the sponsors, or the Institute of Electrical and Electronic Engineers, Inc. · There is NO copyright protection claimed by this publication. However, each presentation is the work of the authors and their respective companies: as such, proper acknowledgement should be made to the appropriate source. Any questions regarding the use of any materials presented should be directed to the author/s or their companies.
Burn-in & Test Socket Workshop Technical Program Session 2 Monday 3/04/02 10:30AM Managing High Frequency Requirements “Optimizing Load Board Design And Modeling For High Frequency Contactors” Jeff Sherry - Johnstech International Corporation “The New YieldPro Array Series Contactor” Julius Botka - Agilent Technologies “Electrical And Mechanical Performance Characterization Of High Frequency Test Sockets” Lisa Steckley - IBM Microelectronics Dr. Hanyi Ding - IBM Microelectronics
Page 1: Burn-in & Test Socket Workshop IEEE
Page 5 and 6: Discussion Topics ▼ Modeling & it
Page 7 and 8: Designing Load Boards for Optimal P
Page 9 and 10: Load Board Effects ▼ Things to im
Page 11 and 12: Crosstalk Improvements ▼ Increase
Page 13 and 14: Load Board Pad Size and Placement 1
Page 15 and 16: Return Loss (dB) 0 -5 -10 -15 -20 -
Page 17 and 18: Model Validation & Performance Exam
Page 19 and 20: Model Validation & Performance Exam
Page 21 and 22: Return Loss (dB) 0 -5 -10 -15 -20 -
Page 23 and 24: Conclusion ▼ Modeling trends can
Page 25 and 26: Brief History • Semiconductor man
Page 27 and 28: Today’s evolution of the business
Page 29 and 30: Design Considerations Problem: Lack
Page 31 and 32: Problem: Excessive and undefined co
Page 33 and 34: Problem: Damage to the bottom of th
Page 35 and 36: Problem: After 100,000 plunges, exc
Page 37 and 38: Problem: Plating will wear away, ox
Page 39 and 40: Problem: Usability issues revolving
Page 41 and 42: Coplanar waveguide substrate with g
Page 43 and 44: Fixture time domain is computed fro
Page 45 and 46: S 11 Gated, coplanar substrate elec
Page 47 and 48: Model of Contacts with Effects of H
Page 49 and 50: S 11 of contact region from model C
Page 51 and 52: Accounting for housing effects * *
Page 53 and 54:
Economic Benefits: • Increase the
Page 55 and 56:
Introduction This presentation summ
Page 57 and 58:
Socket Requirements for Testing RF
Page 59 and 60:
Qualification Process: Determine pa
Page 61 and 62:
Qualification Process: Test Sockets
Page 63 and 64:
Mechanical Analysis: Pogo-style soc
Page 65 and 66:
Mechanical Analysis: S-contact sock
Page 67 and 68:
Mechanical Analysis: Low-profile in
Page 69 and 70:
Mechanical Analysis: Conductive ela
Page 71 and 72:
Qualification Process: Test socket
Page 73 and 74:
Qualification Process: Test socket
Page 75 and 76:
Electrical Performance Simulations
Page 77 and 78:
Electrical Performance Simulations
Page 79:
Recognition of Support John Blondi
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Burn-in & Test Socket Workshop - BiTS Workshop

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