E0286 – VLSI Test VLSI Test

IP Mixture in SOC
H
A
C
D
E
B
F
G
Core A: No compression. No bounding. E: Glue logic.
Core B: No compression. Bounding only. G: SOC level CoDec(s).
Core C: Compression + Bounding
H: SOC bounding.
Core D: Compression only. No bounding. Bounding.
F: DFT logic
• Test IPs – Memory BIST,
scan CoDecs, test mode
controls, E-Fuse, etc.
• Wrappers – Pin-muxing,
analog PMT, 1500 bounding,
etc.