LTC2410 24-Bit No Latency ∆ΣTM ADC with Differential Input and ...

LTC2410APPLICATIO S I FORATIOU W U UThe serial clock mode is selected on the falling edge of CS.To select the external serial clock mode, the serial clock pin(SCK) must be LOW during each CS falling edge.The serial data output pin (SDO) is Hi-Z as long as CS isHIGH. At any time during the conversion cycle, CS may bepulled LOW in order to monitor the state of the converter.While CS is pulled LOW, EOC is output to the SDO pin.EOC␣ =␣ 1 while a conversion is in progress and EOC = 0 ifthe device is in the sleep state. Independent of CS, thedevice automatically enters the low power sleep state oncethe conversion is complete.When the device is in the sleep state (EOC = 0), itsconversion result is held in an internal static shift register.The device remains in the sleep state until the firstrising edge of SCK is seen while CS is LOW. Data is shiftedout the SDO pin on each falling edge of SCK. This enablesexternal circuitry to latch the output on the rising edge ofSCK. EOC can be latched on the first rising edge of SCKand the last bit of the conversion result can be latched onthe 32nd rising edge of SCK. On the 32nd falling edge ofSCK, the device begins a new conversion. SDO goes HIGH(EOC = 1) indicating a conversion is in progress.At the conclusion of the data cycle, CS may remain LOWand EOC monitored as an end-of-conversion interrupt.Alternatively, CS may be driven HIGH setting SDO to Hi-Z.As described above, CS may be pulled LOW at any time inorder to monitor the conversion status.Typically, CS remains LOW during the data output state.However, the data output state may be aborted by pullingCS HIGH anytime between the first rising edge and the32nd falling edge of SCK, see Figure 6. On the rising edgeof CS, the device aborts the data output state and immediatelyinitiates a new conversion. This is useful for systemsnot requiring all 32 bits of output data, aborting aninvalid conversion cycle or synchronizing the start of aconversion.External Serial Clock, 2-Wire I/OThis timing mode utilizes a 2-wire serial I/O interface. Theconversion result is shifted out of the device by an externallygenerated serial clock (SCK) signal, see Figure 7. CSmay be permanently tied to ground, simplifying the userinterface or isolation barrier.The external serial clock mode is selected at the end of thepower-on reset (POR) cycle. The POR cycle is concludedapproximately 0.5ms after V CC exceeds 2.2V. The levelapplied to SCK at this time determines if SCK is internal orexternal. SCK must be driven LOW prior to the end of PORin order to enter the external serial clock timing mode.REFERENCEVOLTAGE0.1V TO V CCANALOG INPUT RANGE–0.5V REF TO 0.5V REF2.7V TO 5.5V1µF2V CC F O14LTC24103REF + 13SCK4REF –561, 7, 8, 9, 10, 15, 16IN +IN –GNDSDO12CS11V CC= 50Hz REJECTION= EXTERNAL OSCILLATOR= 60Hz REJECTION3-WIRESPI INTERFACECSTEST EOCTEST EOCBIT 31BIT 30BIT 29BIT 28BIT 27 BIT 26BIT 5BIT 0TEST EOCSDOHi-ZHi-ZEOCSIGMSBLSBSUB LSBHi-ZSCK(EXTERNAL)CONVERSIONSLEEP DATA OUTPUT CONVERSION2410 F05Figure 5. External Serial Clock, Single Cycle Operation17