LTC2410 24-Bit No Latency ∆ΣTM ADC with Differential Input and ...

LTC2410APPLICATIO S I FORINL (ppm OF V REF )15129630–3–6–9–12ATIOU W U UR SOURCE = 100ΩR SOURCE = 1000ΩR SOURCE = 500Ω–15–0.5–0.4–0.3–0.2–0.1 0 0.1 0.2 0.3 0.4 0.5V INDIF /V REFDIFV CC = 5VREF+ = 5VREF– = GNDV INCM = 0.5 • (IN + + IN – ) = 2.5VF O = GNDC REF = 10µFT A = 25°C2410 F26Figure 26. INL vs Differential Input Voltage (V IN = IN + – IN – )and Reference Source Resistance (R SOURCE at REF + and REF – forLarge C REF Values (C REF ≥ 1µF)The magnitude of the dynamic reference current dependsupon the size of the very stable internal sampling capacitorsand upon the accuracy of the converter samplingclock. The accuracy of the internal clock over the entiretemperature and power supply range is typical better than0.5%. Such a specification can also be easily achieved byan external clock. When relatively stable resistors(50ppm/°C) are used for the external source impedanceseen by REF + and REF – , the expected drift of the dynamiccurrent gain error will be insignificant (about 1% of itsvalue over the entire temperature and voltage range). Evenfor the most stringent applications a one-time calibrationoperation may be sufficient.In addition to the reference sampling charge, the referencepins ESD protection diodes have a temperature dependentleakage current. This leakage current, nominally 1nA(±10nA max), results in a small gain error. A 100Ω sourceresistance will create a 0.05µV typical and 0.5µV maximumfull-scale error.Output Data RateWhen using its internal oscillator, the LTC2410 can produceup to 7.5 readings per second with a notch frequencyof 60Hz (F O = LOW) and 6.25 readings per second with anotch frequency of 50Hz (F O = HIGH). The actual outputdata rate will depend upon the length of the sleep and dataoutput phases which are controlled by the user and whichcan be made insignificantly short. When operated with anexternal conversion clock (F O connected to an externaloscillator), the LTC2410 output data rate can be increasedas desired. The duration of the conversion phase is 20510/f EOSC . If f EOSC = 153600Hz, the converter behaves as if theinternal oscillator is used and the notch is set at 60Hz.There is no significant difference in the LTC2410 performancebetween these two operation modes.An increase in f EOSC over the nominal 153600Hz willtranslate into a proportional increase in the maximumoutput data rate. This substantial advantage is neverthelessaccompanied by three potential effects, which mustbe carefully considered.First, a change in f EOSC will result in a proportional changein the internal notch position and in a reduction of theconverter differential mode rejection at the power linefrequency. In many applications, the subsequent performancedegradation can be substantially reduced by relyingupon the LTC2410’s exceptional common mode rejectionand by carefully eliminating common mode to differentialmode conversion sources in the input circuit. Theuser should avoid single-ended input filters and shouldmaintain a very high degree of matching and symmetry inthe circuits driving the IN + and IN – pins.Second, the increase in clock frequency will increaseproportionally the amount of sampling charge transferredthrough the input and the reference pins. If large externalinput and/or reference capacitors (C IN , C REF ) are used, theprevious section provides formulae for evaluating theeffect of the source resistance upon the converter performancefor any value of f EOSC . If small external input and/or reference capacitors (C IN , C REF ) are used, the effect ofthe external source resistance upon the LTC2410 typicalperformance can be inferred from Figures 17, 18, 22 and23 in which the horizontal axis is scaled by 153600/f EOSC .Third, an increase in the frequency of the external oscillatorabove 460800Hz (a more than 3× increase in the outputdata rate) will start to decrease the effectiveness of theinternal autocalibration circuits. This will result in a progressivedegradation in the converter accuracy and linear-29