LTC2410 24-Bit No Latency ∆ΣTM ADC with Differential Input and ...

LTC2410APPLICATIO S I FOR26ATIOU W U UFor relatively small values of input capacitance (C IN 0.01µF) may berequired in certain configurations for antialiasing or generalinput signal filtering. Such capacitors will average theinput sampling charge and the external source resistancewill see a quasi constant input differential impedance.When F O = LOW (internal oscillator and 60Hz notch), thetypical differential input resistance is 1.8MΩ which willgenerate a gain error of approximately 0.28ppm for eachohm of source resistance driving IN + or IN – . When F O =HIGH (internal oscillator and 50Hz notch), the typicaldifferential input resistance is 2.16MΩ which will generatea gain error of approximately 0.23ppm for each ohm ofsource resistance driving IN + or IN – . When F O is driven byan external oscillator with a frequency f EOSC (externalconversion clock operation), the typical differential inputresistance is 0.28 • 10 12 /f EOSC Ω and each ohm ofsource resistance driving IN + or IN – will result in1.78 • 10 –6 • f EOSC ppm gain error. The effect of the sourceresistance on the two input pins is additive with respect tothis gain error. The typical +FS and –FS errors as a functionof the sum of the source resistance seen by IN + and IN – forlarge values of C IN are shown in Figures 19 and 20.In addition to this gain error, an offset error term may alsoappear. The offset error is proportional with the mismatchbetween the source impedance driving the two input pinsIN + and IN – and with the difference between the input andreference common mode voltages. While the input drivecircuit nonzero source impedance combined with theconverter average input current will not degrade the INLperformance, indirect distortion may result from the modulationof the offset error by the common mode componentof the input signal. Thus, when using large C IN capacitorvalues, it is advisable to carefully match the source impedanceseen by the IN + and IN – pins. When F O = LOW(internal oscillator and 60Hz notch), every 1Ω mismatchin source impedance transforms a full-scale commonmode input signal into a differential mode input signal of0.28ppm. When F O = HIGH (internal oscillator and 50Hznotch), every 1Ω mismatch in source impedance transformsa full-scale common mode input signal into adifferential mode input signal of 0.23ppm. When F O isdriven by an external oscillator with a frequency f EOSC ,every 1Ω mismatch in source impedance transforms afull-scale common mode input signal into a differentialmode input signal of 1.78 • 10 –6 • f EOSC ppm. Figure 21shows the typical offset error due to input common modevoltage for various values of source resistance imbalancebetween the IN + and IN – pins when large C IN values areused.If possible, it is desirable to operate with the input signalcommon mode voltage very close to the reference signalcommon mode voltage as is the case in the ratiometricmeasurement of a symmetric bridge. This configurationeliminates the offset error caused by mismatched sourceimpedances.The magnitude of the dynamic input current depends uponthe size of the very stable internal sampling capacitors andupon the accuracy of the converter sampling clock. Theaccuracy of the internal clock over the entire temperatureand power supply range is typical better than 0.5%. Sucha specification can also be easily achieved by an externalclock. When relatively stable resistors (50ppm/°C) areused for the external source impedance seen by IN + andIN – , the expected drift of the dynamic current, offset andgain errors will be insignificant (about 1% of their respectivevalues over the entire temperature and voltage range).Even for the most stringent applications, a one-timecalibration operation may be sufficient.