LTC2410 24-Bit No Latency ∆ΣTM ADC with Differential Input and ...

LTC2410APPLICATIO S I FORATIOU W U USimultaneous Sampling with Two LTC2410sOne such application is synchronizing multiple LTC2410s,see Figure 45. The start of conversion is synchronized tothe rising edge of CS. In order to synchronize multipleLTC2410s, CS is a common input to all the ADCs.To prevent the converters from autostarting a new conversionat the end of data output read, 31 or fewer SCKclock signals are applied to the LTC2410 instead of 32 (the32nd falling edge would start a conversion). The exacttiming and frequency for the SCK signal is not criticalsince it is only shifting out the data. In this case, twoLTC2410’s simultaneously start and end their conversioncycles under the external control of CS.Increasing the Output Rate Using Mulitple LTC2410sA second application uses multiple LTC2410s to increasethe effective output rate by 4×, see Figure 46. In this case,four LTC2410s are interleaved under the control of separateCS signals. This increases the effective output ratefrom 7.5Hz to 30Hz (up to a maximum of 60Hz). Additionally,the one-shot output spectrum is unfolded allowingfurther digital signal processing of the conversion results.SCK and SDO may be common to all four LTC2410s. Thefour CS rising edges equally divide one LTC2410 conversioncycle (7.5Hz for 60Hz notch frequency). In order tosynchronize the start of conversion to CS, 31 or less SCKclock pulses must be applied to each ADC.Both the synchronous and 4× output rate applications usethe external serial clock and single cycle operation withreduced data output length (see Serial Interface TimingModes section and Figure 6). An external oscillator clockis applied commonly to the F O pin of each LTC2410 inorder to synchronize the sampling times. Both circuitsmay be extended to include more LTC2410s.SCK2SCK1LTC2410#1LTC2410#2EXTERNAL OSCILLATOR(153,600HZ)V CCF OV CCF OREF +SCKREF +SCKµCONTROLLERREF –IN +SDOCSREF –IN +SDOCSIN –IN –GNDGNDCSSDO1SDO2V REF +V REF –CSSCK131 OR LESS CLOCK CYCLESSCK231 OR LESS CLOCK CYCLESSDO1SDO22410 F45Figure 45. Synchronous Conversion—Extendable35