LTC2410 24-Bit No Latency ∆ΣTM ADC with Differential Input and ...

LTC2410APPLICATIO S I FORSAMPLE RATE (Hz)t SAMPLE (SEC)SUPPLY CURRENT (µA RMS )765432101ATIOU W U UV CC = 5VV CC = 3V10 100 1000 10000 100000CAPACITANCE ON CS (pF)2400 F12Figure 12. CS Capacitance vs t SAMPLE876V CC = 5V5V CC = 3V432100 10 100 1000 10000 100000CAPACITANCE ON CS (pF)2400 F13Figure 13. CS Capacitance vs Output Rate300250 V CC = 5V200V CC = 3V1501005001 10 100 1000 10000 100000CAPACITANCE ON CS (pF)2400 F14Figure 14. CS Capacitance vs Supply CurrentCS is discharging; therefore, the internal serial clocktiming mode is automatically selected if SCK is floating. Itis important to ensure there are no external drivers pullingSCK LOW while CS is discharging.PRESERVING THE CONVERTER ACCURACYThe LTC2410 is designed to reduce as much as possiblethe conversion result sensitivity to device decoupling,PCB layout, antialiasing circuits, line frequency perturbationsand so on. Nevertheless, in order to preserve theextreme accuracy capability of this part, some simpleprecautions are desirable.Digital Signal LevelsThe LTC2410’s digital interface is easy to use. Its digitalinputs (F O , CS and SCK in External SCK mode of operation)accept standard TTL/CMOS logic levels and the internalhysteresis receivers can tolerate edge rates as slow as100µs. However, some considerations are required to takeadvantage of the exceptional accuracy and low supplycurrent of this converter.The digital output signals (SDO and SCK in Internal SCKmode of operation) are less of a concern because they arenot generally active during the conversion state.While a digital input signal is in the range 0.5V to(V CC ␣ –␣ 0.5V), the CMOS input receiver draws additionalcurrent from the power supply. It should be noted that,when any one of the digital input signals (F O , CS and SCKin External SCK mode of operation) is within this range, theLTC2410 power supply current may increase even if thesignal in question is at a valid logic level. For micropoweroperation, it is recommended to drive all digital inputsignals to full CMOS levels [V IL < 0.4V and V OH >(V CC – 0.4V)].During the conversion period, the undershoot and/orovershoot of a fast digital signal connected to the LTC2410pins may severely disturb the analog to digital conversionprocess. Undershoot and overshoot can occur because ofthe impedance mismatch at the converter pin when thetransition time of an external control signal is less thantwice the propagation delay from the driver to LTC2410.For reference, on a regular FR-4 board, signal propagation23