hbrisc2 - Microelectronics

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BRISC Architecture Overview: Radiation Effects SEU (Single Event Upset) Bit flipping on storage cells (register, memory cell…) Caused by heavy ions radiations Critical components in typical HBRISC board: CPU registers, SRAM,Flash/EEPROMLow voltage power busSRAM(APPLICATION)programbusCPUHBrisc2Power drivecommandSensorexcitation(E)EPROM(BACK-UP)I/ObusADC cntrlSensors signalsADCTN0342-Iss10.pptAll right reserved: Disclosure to third parties of this document or any part thereof, or the use of any information contained therein for purposes other than provided for by this document, is not permitted exceptwith prior and express written permission of S.A.B.C.A.06/12/200412
BRISC Architecture Overview: Radiation Effects BRISC SEU-hardened architecture: instruction/data SRAM protectionProgrambus46/INSTRUCTION REGISTERON-CHIP SEUERRORDETECTION/CORRECTIONUNITUnit AGLOBALREGISTERSREGISTERBANKFLOATINGPOINTUNITADCinterfaceI/OinterfaceINSTRUCTIONDECODERGLOBALREGISTERSREGISTERBANKFLOATINGPOINTUNITCRCcheck 32+8Unit BON-CHIP MEMORYSEU ERRORCORRECTIONUNITGLOBALREGISTERSFIXED POINTARITHMETICUNITRIOUnit SURPADON-CHIP PERIPHERALINTERFACEmotorPWMHBRISC2COREPeripheralbusexcitationPWMSerialFast link 16ADDRESSREGISTERINSTRUCTIONSEQUENCERBOOTROMREGISTERSSEUDETECTION/CORRECTIONUNITSerial port(SPI)softwaretimerAddressbus4/• “LIVE” CORRECTION BEFOREINSTRUCTION DECODING• AUTOMATIC SRAM CORRECTIONON HBRISC2 STOLEN CYCLES• MODIFIED HAMMING CODE detects and corrects all 1-bit errors detects all 2-bit errors detects part of multiple-bit errors• NO ADDED DELAY DURINGINSTRUCTION FETCH• HARDWARE REPORTINGHBRISC2PERIPHERAL 18 6 2 1TN0342-Iss10.pptAll right reserved: Disclosure to third parties of this document or any part thereof, or the use of any information contained therein for purposes other than provided for by this document, is not permitted exceptwith prior and express written permission of S.A.B.C.A.06/12/200413
Page 1 and 2: GSTP2-IMCMESTEC/Contract N° 13492/
Page 3 and 4: BRISC Architecture Overview Targete
Page 5 and 6: BRISC Architecture Overview Provide
Page 7 and 8: BRISC Architecture OverviewProgramb
Page 9 and 10: BRISC Architecture Overview On-chip
Page 11: BRISC Architecture Overview: Radiat
Page 15 and 16: BRISC Architecture Overview: Radiat
Page 17 and 18: Brisc Architecture Overview: ASIC T
Page 19 and 20: IMCM ASIC -HBRISC2- development log
Page 21 and 22: NOT USEDNOT USEDBXADD(0)BXADD(1)BXA
Page 23 and 24: Hbrisc2 Circuit Validation Strategy
Page 31 and 32: HBRISC2 application development pro
Page 33 and 34: Production chain of HBRISC2 applica
Page 36 and 37: Validation of the synthesiser The s
Page 38 and 39: The macro library The macros are cl
Page 40 and 41: The unit test tool Total_nw is a to
Page 42 and 43: Validation of the Simulink library
Page 44 and 45: IMCM Demonstration Application The
Page 46 and 47: IMCM Demonstration Application The
Page 48 and 49: VEGA TVC IPDUAVUMZ 9Z 23P 80EM TVC
Page 50 and 51: GSTP3 HPEA & GSTP4 Reaction Sphere,
Page 52: IMCM ConclusionHBRISC2 and its deve

hbrisc2 - Microelectronics

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