hbrisc2 - Microelectronics

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IMCM Project Assessment BRISC architecture Targeted applications Architecture overview IMCM ASIC HBRISC2 development logic HBRISC2 validation strategy HBRISC2 application development process Production& validation tools Synthesizer Macro Library Assembler Unit test tool Validation of the macros and Simulink library Win-Seracq tool IMCM demonstration application HBRISC2 perspectives Current and coming applications Towards HBRISC2 Application+ Tool IMCM conclusionTN0342-Iss10.pptAll right reserved: Disclosure to third parties of this document or any part thereof, or the use of any information contained therein for purposes other than provided for by this document, is not permitted exceptwith prior and express written permission of S.A.B.C.A.06/12/20042
BRISC Architecture Overview Targeted to the command of high performance electrical motors in criticalapplications True from the very first release of BRISC & continuously improved Application key requirements Versatile, standard product Hard real-time, with tight HW-SW synchronization Fully predictable execution time No corner-case caused by the use of digital domain High visibility on the internal functioning Architecture impact Data path optimized for vector control, motor modeling... Intrinsic high computing power: floating multiplication, division (HBRISC2) Saturating arithmetic (no exceptions) RISC machine High digital function integration (avoid glue logic, on-board µP or FPGA...) High Speed serial link dedicated to reporting Straightforward compatibility to standard components (ADC, RAM, Flash, EEPROM,...)TN0342-Iss10.pptAll right reserved: Disclosure to third parties of this document or any part thereof, or the use of any information contained therein for purposes other than provided for by this document, is not permitted exceptwith prior and express written permission of S.A.B.C.A.06/12/20043
Page 1: GSTP2-IMCMESTEC/Contract N° 13492/
Page 5 and 6: BRISC Architecture Overview Provide
Page 7 and 8: BRISC Architecture OverviewProgramb
Page 9 and 10: BRISC Architecture Overview On-chip
Page 11 and 12: BRISC Architecture Overview: Radiat
Page 17 and 18: Brisc Architecture Overview: ASIC T
Page 19 and 20: IMCM ASIC -HBRISC2- development log
Page 21 and 22: NOT USEDNOT USEDBXADD(0)BXADD(1)BXA
Page 23 and 24: Hbrisc2 Circuit Validation Strategy
Page 31 and 32: HBRISC2 application development pro
Page 33 and 34: Production chain of HBRISC2 applica
Page 36 and 37: Validation of the synthesiser The s
Page 38 and 39: The macro library The macros are cl
Page 40 and 41: The unit test tool Total_nw is a to
Page 42 and 43: Validation of the Simulink library
Page 44 and 45: IMCM Demonstration Application The
Page 46 and 47: IMCM Demonstration Application The
Page 48 and 49: VEGA TVC IPDUAVUMZ 9Z 23P 80EM TVC
Page 50 and 51: GSTP3 HPEA & GSTP4 Reaction Sphere,
Page 52:
IMCM ConclusionHBRISC2 and its deve
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hbrisc2 - Microelectronics

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