hbrisc2 - Microelectronics

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Validation of the synthesiser The synthesiser is a single executable, but is divided in several modules: A parser that reads the main input files and builds an equivalent objectstructure in memory A sorter that orders the blocks and slots. An assigner that gives units and registers to the macros, so the macros callscan be fulfilled. A generator that produces the final code, and inserts intermediate macrocalls to ensure integrity of the information. Specific test cases have been created to check that each of thesemodules worked correctly. A test case with the same complexity as the application has beensynthesised and its generated code carefully checked. Integration and validation tests have used code generated by thesynthesiser.TN0342-Iss10.pptAll right reserved: Disclosure to third parties of this document or any part thereof, or the use of any information contained therein for purposes other than provided for by this document, is not permitted exceptwith prior and express written permission of S.A.B.C.A.06/12/200436
Macro libraryControllerRegulationVCTCutPowerIfStandby3SC1Dimmer3SC1Limiter2SC1OverflowWithSaturationSC1PositionToSpeed3SCLActuatorPositionVCTActuatorPositionSCLElectricalAngle3SCLElectricalAngleSCLMultiplicationVCTModulusLimiter3VCTNormalizeFundamental2SCLBackwardEulerLowPass3SCLBackwardEulerPI2SCLCorrectAfterRegulator2SCLGainSCLRegulationErrorVCTMotorCreateDutyCyclesVCTMotorDecoupledCurrentControl2VCTMotorNeutralModulationVCTLvdtToPositionVCTSecondOrderFilter2VCTClarkeDirectVCTClarkeInverseVCTGainOffset2VCTParkDirectVCTParkInverseVCTRamp3VCTFilter52MathSCLOffsetGain2SCLOneBySCLOneBySqrtVCTCartesianToPolarVCTArcTanVCTCosSinSCLAdd1553 stackUtilityremovedANYCopyRegister*ANYCopyRegisterA*ANYCopyRegisterB*ANYCopyRegisterSU*ANYLoadFromMemINTRepeatLoop3*ANYLoadImmediateINTDualInputOrUNDCondFalseJumpTo*UNDCondTrueJumpTo*SCLDualInputSelectorSCLQuantizer3SGLSaveImmediateToMemSGLSingleSaveToMemSCLDiffTrueJumpTo*SCLDiffFalseJumpTo*UNDGoBank*UNDGoNextBank*UNDGoPreviousBank*UNDJumpTo*SC1IsGreater3SC1IsGreaterEqual3SC1IsLower3SC1IsLowerEqual3INTUniToggle3SC1UniToggle3HWADCSCLFormatData12bitsAsymSCLFormatData12bitsSymSGLADCInit*ANYReadADCSample*SGLSelectADCMux*SGLSelectADCMux3*VCTMuxSwitchAdcSampleVCTMuxSwitchAdcSample3IO InterfaceSGLIOIfaceInit*PWMSC1BriscPwmSymOutput3VCTBriscPwmSymOutput3SGLPWMInit*UNDStartPwmTimer*UNDStartMainTimer*VCTBriscSymPwmGen3VCTSavePwmIO*SC1SavePwmIO*ExcitationSGLExcitationInit*UNDExcitationTicSelect*Serial LinkSGLTransmitFSLINTTransmitFSLAINTTransmitFSLBUNDSerialInit*TN0342-Iss10.pptSofwaretimerSGLSoftTimerInit*UNDStartSoftTimer*UNDWaitSynchro*UNDWaitSynchroDelayed*SPISCLReadSPIINTWriteSPIAINTWriteSPIBINTReadSPIRIO AccessANYLoadIO3SGLSaveIO3SGLSaveIO*All right reserved: Disclosure to third parties of this document or any part thereof, or the use of any information contained therein for purposes other than provided for by this document, is not permitted exceptwith prior and express written permission of S.A.B.C.A.06/12/200437
Page 1 and 2: GSTP2-IMCMESTEC/Contract N° 13492/
Page 3 and 4: BRISC Architecture Overview Targete
Page 5 and 6: BRISC Architecture Overview Provide
Page 7 and 8: BRISC Architecture OverviewProgramb
Page 9 and 10: BRISC Architecture Overview On-chip
Page 11 and 12: BRISC Architecture Overview: Radiat
Page 17 and 18: Brisc Architecture Overview: ASIC T
Page 19 and 20: IMCM ASIC -HBRISC2- development log
Page 21 and 22: NOT USEDNOT USEDBXADD(0)BXADD(1)BXA
Page 23 and 24: Hbrisc2 Circuit Validation Strategy
Page 31 and 32: HBRISC2 application development pro
Page 33 and 34: Production chain of HBRISC2 applica
Page 38 and 39: The macro library The macros are cl
Page 40 and 41: The unit test tool Total_nw is a to
Page 42 and 43: Validation of the Simulink library
Page 44 and 45: IMCM Demonstration Application The
Page 46 and 47: IMCM Demonstration Application The
Page 48 and 49: VEGA TVC IPDUAVUMZ 9Z 23P 80EM TVC
Page 50 and 51: GSTP3 HPEA & GSTP4 Reaction Sphere,
Page 52: IMCM ConclusionHBRISC2 and its deve

hbrisc2 - Microelectronics

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