hbrisc2 - Microelectronics

NOT USEDNOT USEDBXADD(0)BXADD(1)BXADD(2)D_CBARVSSVCSPIBOOT_MSTRMAIN_CKPROGOUT(0)ADC_MUXSELECT(0)ADC_MUXSELECT(1)VSSVCBXADD(3)BXADD(4)BXADD(5)PROGOUT(1)PROGOUT(2)PROGOUT(3)R_WBADC_MUXSELECT(2)VSSVCBXADD(6)BXADD(7)BXADD(8)SERIAL_CLKSERI AL_DATAADC_MUXSELECT(3)VSSVCBXADD(9)BXADD( 10)BXADD( 1)SI OP_CSBAR(0)SI OP_CSBAR(1)SI OP_OEBAR(0)VSSVDBXADD( 12)BXADD( 13)BXADD( 14)SI OP_CSBAR(2)SI OP_CSBAR(3)SI OP_OEBAR(1)VSSVCBXADD( 15)NOT USEDSI OP_OEBAR(2)SI OP_OEBAR(3)ADCIOBUS(0)ADCIOBUS(1)ADCIOBUS(2)VSSVCSIOP_WE BAR(0)SIOP_WE BAR(1)VSSVCNOT USEDNOT USED12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364NOT USEDNOT USED25 625 5N O T US E D 656VCCVSSSEL_BOOTASVCCVSSRESET_BARDSBXI O(0)BXI O(1)BXI O(2)BXI O(3)BXI O(4)BXI O(5)VCCVSSBXI O(6)BXI O(7)BXI O(8)BXI O(9)BXI O(10)BXI O(11)BXI O(12)VCCVSSBXI O(13)BXI O(14)BXI O(15)BXI O(16)BXI O(17)BXI O(18)BXI O(19)VCCVSSBXI O(20)BXI O(21)BXI O(22)BXI O(23)BXI O(24)BXI O(25)BXI O(26)VCCVSSBXI O(27)BXI O(28)BXI O(29)BXI O(30)BXI O(31)BXI O(32)BXI O(33)VCCVSSBXI O(34)BXI O(35)VCCVSSBXI O(36)BXI O(37)BXI O(38)NOT USEDNOT USEDNOT USED25 425 325 225 125024924824724624524424324224124023923823723623523423323223123029282726252423222120219218217216215214213212211210209208207206205204203202201200199198197196195194193N O T US E DS IO P _ W E B A R (2 ) 67S IO P _ W E B A R (3 )6869707172737475767A D CI O B U S (3 )A D CI O B U S (4 )VS SV C CA D CI O B U S (5 )A D CI O B U S (6 )A D CI O B U S (7 )A D CI O B U S (8 )VS SV C CA D CI O B U S (9 )A D C IO B U S (1 0 )78798081828384858687889909192939495969798910 010 110 210 310 410 510 610 710 810 91 01 11 21 31 41 51 61 71 81 912 012 112 212 312 412 512 612 712 8A D C IO B U S (1 1 )A D C IO B U S (1 2 )A D C IO B U S (1 3 )A D C IO B U S (1 4 )A D C IO B U S (1 5 )VS SV C CA DC _ E O C B A R (0 )A DC _ E O C B A R (1 )A DC _ E O C B A R (2 )A DC _ E O C B A R (3 )T D IT D OT C KT M ST RS TN O T US E DN O T US E DS IO P _ A D D (0 )S IO P _ A D D (1 )S IO P _ A D D (2 )S IO P _ A D D (3 )S IO P _ A D D (4 )S IO P _ A D D (5 )S IO P _ A D D (6 )S IO P _ A D D (7 )S IO P _ A D D (8 )S IO P _ A D D (9 )S IO P _ A D D (1 0 )S IO P _ A D D (1 1 )S IO P _ A D D (1 2 )VS SV C CS IO P _ A D D (1 3 )S IO P _ A D D (1 4 )S IO P _ A D D (1 5 )S IO P _ A D D (1 6 )S IO P _ A D D (1 7 )S O FT _ T ICS O F T _T IC _ D E L AY E DVS SV C CS Y N CH R _ T ICT ES TT E S T _C L KT E S T _S EN O T US E DN O T US E D192191190189188187186185184183182181180179178177176175174173172171170169168167166165164163162161160159158157156155154153152151150149148147146145144143142141140139138137136135134133132131130129NOT USEDNOT USEDNOT USEDINT_BARNOT USEDNOT USEDVCCVSSNOT USEDNOT USEDSE3_BSE3_ASE2_BSE2_AVCCVSSSE1_BSE1_ASEU_ERRORSEU_CORR_ISEU_CORR_EM3_PWM3HM3_PWM3LM3_PWM2HM3_PWM2LM3_PWM1HM3_PWM1LNOT USEDNOT USEDM2_PWM3HM2_PWM3LM2_PWM2HM2_PWM2LM2_PWM1HM2_PWM1LVCCVSSUPLOAD_ERUPLOAD_IPIACKBARCRC_CHECKODD_CKM1_PWM3HM1_PWM3LM1_PWM2HM1_PWM2LM1_PWM1HM1_PWM1LSPI _OUTSPI _CSBARSPI _I NSPI _CLKADC_CS(3)ADC_CS(2)ADC_CS(1)ADC_CS(0)VCCVSSVCCVSSADC_SOCADC_R_CNOT USEDNOT USEDIMCM ASIC -HBRISC2- development logic Design FlowVHDLDesigntestbenchRTLsimulationCADENCE NC-VHDLFPGALogicsynthesisconstraintspre-layouttiming fileASICLogicsynthesisnetlistsimulationSYNOPSYSDESIGN COMPILER (ASIC)FPGA COMPILER 2 (FPGA)Scan/JTAGinsertionATMEL TOOLS (ASIC)HBRISC2post-layouttiming fileLayoutpost-layoutsimulationconstraintspost-layouttiming fileLayoutsign-offsimulationATMEL TOOLS (ASIC)ACTEL ASICMASTER (FPGA)To FPGAtest boardstatictiminganalysisTo foundrySYNOPSYSDESIGN TIME (ASIC)TN0342-Iss10.pptAll right reserved: Disclosure to third parties of this document or any part thereof, or the use of any information contained therein for purposes other than provided for by this document, is not permitted exceptwith prior and express written permission of S.A.B.C.A.06/12/200421