hbrisc2 - Microelectronics

BRISC Architecture Overview: Radiation Effects BRISCProgramAddressSEU-hardened architecture: boot rom protectionbusINSTRUCTION REGISTERON-CHIP SEUERRORDETECTION/CORRECTIONUNITUnit AGLOBALREGISTERSREGISTERBANKFLOATINGPOINTUNIT 32+7INSTRUCTIONDECODERUnit BGLOBALREGISTERSREGISTERBANKFLOATINGPOINTUNITON-CHIP MEMORYSEU ERRORCORRECTIONUNITGLOBALREGISTERSFIXED POINTARITHMETICUNITRIOHBRISC2COREUnit SURPAD 16ADDRESSREGISTERINSTRUCTIONSEQUENCERBOOTROMREGISTERSSEUDETECTION/CORRECTIONUNITbus• BASED ON CRC BLOCK• ONLY ERROR DETECTION ISPOSSIBLE (NO CORRECTIONPERFORMED)• HARDWARE AND SOFTWAREREPORTING46/ADCinterfaceI/OinterfaceON-CHIP PERIPHERALINTERFACEPeripheralbusProg.outputsSerial port(SPI)4/3//1CRCcheckmotorPWMexcitationPWMSerialFast linksoftwaretimerTN0342-Iss10.pptHBRISC2PERIPHERAL 18 6 2 2All right reserved: Disclosure to third parties of this document or any part thereof, or the use of any information contained therein for purposes other than provided for by this document, is not permitted exceptwith prior and express written permission of S.A.B.C.A.06/12/200416