hbrisc2 - Microelectronics

Hbrisc2 Circuit Validation Strategy: Hbrisc2 Status PRE-layout frequency: 50 MHz POST-layout frequency: 54 MHz Design area: 260 074 cells ATPG Test coverage: 97.53 % cells sites used: 54.05% IO sites used: 40.29% SEU Flip-flop count: 7039 Non-SEU flip-flops: 597 Latches count: 39 Cells distribution:CORE10% 2%SCAN88%JTAGTN0342-Iss10.pptAll right reserved: Disclosure to third parties of this document or any part thereof, or the use of any information contained therein for purposes other than provided for by this document, is not permitted exceptwith prior and express written permission of S.A.B.C.A.06/12/200430