hbrisc2 - Microelectronics

BRISC Architecture Overview: Radiation Effects BRISC SEU-hardened architecture: on-chip (bank register) SRAM protectionProgrambusINSTRUCTION REGISTERON-CHIP SEUERRORDETECTION/CORRECTIONUNITUnit AGLOBALREGISTERSREGISTERBANKFLOATINGPOINTUNIT 32+8INSTRUCTIONDECODERUnit BGLOBALREGISTERSREGISTERBANKFLOATINGPOINTUNITON-CHIP MEMORYSEU ERRORCORRECTIONUNITGLOBALREGISTERSFIXED POINTARITHMETICUNITRIOHBRISC2COREUnit SURPAD 16ADDRESSREGISTERINSTRUCTIONSEQUENCERBOOTROMREGISTERSSEUDETECTION/CORRECTIONUNITAddressbus• DETECTION/CORRECTION MADEDURING INSTRUCTION EXECUTION• ON ERROR, RE-EXECUTIONFOLLOWS CORRECTION• MODIFIED HAMMING CODE AS PEREXTERNAL SRAM• HARDWARE REPORTING46/ADCinterfaceI/OinterfaceON-CHIP PERIPHERALINTERFACEPeripheralbusSerial port(SPI)4/CRCcheckmotorPWMexcitationPWMSerialFast linksoftwaretimerHBRISC2PERIPHERAL 18 6 2 1TN0342-Iss10.pptAll right reserved: Disclosure to third parties of this document or any part thereof, or the use of any information contained therein for purposes other than provided for by this document, is not permitted exceptwith prior and express written permission of S.A.B.C.A.06/12/200414